Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9947765 | Dummy gate placement methodology to enhance integrated circuit performance | Younsung Choi, Shashank S. Ekbote | 2018-04-17 |
| 9496142 | Dummy gate placement methodology to enhance integrated circuit performance | Younsung Choi, Shashank S. Ekbote | 2016-11-15 |
| 9054214 | Methodology of forming CMOS gates on the secondary axis using double-patterning technique | Scott Jessen | 2015-06-09 |
| 8791527 | Device layout in integrated circuits to reduce stress from embedded silicon—germanium | — | 2014-07-29 |
| 8748256 | Integrated circuit having silicide block resistor | Song Zhao, Shashank S. Ekbote, Youn Sung Choi | 2014-06-10 |
| 8669775 | Scribe line test modules for in-line monitoring of context dependent effects for ICs including MOS devices | Youn Sung Choi, Oluwamuyiwa Oluwagbemiga Olubuyide | 2014-03-11 |
| 8664968 | On-die parametric test modules for in-line monitoring of context dependent effects | Thomas J. Aton, Kayvan Sadra, Oluwamuyiwa Oluwagbemiga Olubuyide, Youn Sung Choi | 2014-03-04 |
| 8595656 | Marker layer to facilitate mask build with interactive layers | Thomas J. Aton, Robert L. Pitts | 2013-11-26 |
| 8513105 | Flexible integration of logic blocks with transistors of different threshold voltages | James Walter Blatchford | 2013-08-20 |
| 8438526 | Method for minimizing transistor and analog component variation in CMOS processes through design rule restrictions | Younsung Choi, Oluwamuyiwa Oluwagbemiga Olubuyide | 2013-05-07 |
| 8183117 | Device layout in integrated circuits to reduce stress from embedded silicon-germanium | — | 2012-05-22 |
| 6143594 | On-chip ESD protection in dual voltage CMOS | Alwin Tsao, Vikas Gupta, E. Ajith Amerasekera, David B. Spratt, Timothy A. Rost | 2000-11-07 |
| 6137144 | On-chip ESD protection in dual voltage CMOS | Alwin Tsao, Vikas Gupta, E. Ajith Amerasekera, David B. Spratt, Timothy A. Rost | 2000-10-24 |