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Electrostatic discharge device and method |
Vikas Gupta, Stanton Petree Ashburn |
2008-11-25 |
| 6628493 |
System and method for electrostatic discharge protection using lateral PNP or PMOS or both for substrate biasing |
Zhiliang Chen, Thomas A. Vrotsos |
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| 6530064 |
Method and apparatus for predicting an operational lifetime of a transistor |
Karthik Vasanth, Shian Aur, Sharad Saxena, Joseph C. Davis, Richard G. Burch |
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| 6469353 |
Integrated ESD protection circuit using a substrate triggered lateral NPN |
Charvaka Duvvury |
2002-10-22 |
| 6433392 |
Electrostatic discharge device and method |
Vikas Gupta, Stanton Petree Ashburn |
2002-08-13 |
| 6143594 |
On-chip ESD protection in dual voltage CMOS |
Alwin Tsao, Vikas Gupta, Gregory Charles Baldwin, David B. Spratt, Timothy A. Rost |
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On-chip ESD protection in dual voltage CMOS |
Alwin Tsao, Vikas Gupta, Gregory Charles Baldwin, David B. Spratt, Timothy A. Rost |
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| 6081002 |
Lateral SCR structure for ESD protection in trench isolated technologies |
Bernhard H. Andresen, Amitava Chatterjee |
2000-06-27 |
| 6040968 |
EOS/ESD protection for high density integrated circuits |
Charvaka Duvvury, Sridhar Ramaswamy |
2000-03-21 |
| 5949094 |
ESD protection for high density DRAMs using triple-well technology |
— |
1999-09-07 |
| 5930094 |
Cascoded-MOS ESD protection circuits for mixed voltage chips |
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| 5804860 |
Integrated lateral structure for ESD protection in CMOS/BiCMOS technologies |
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1998-09-08 |
| 5793083 |
Method for designing shallow junction, salicided NMOS transistors with decreased electrostatic discharge sensitivity |
Vincent M. McNeil, Mark S. Rodder |
1998-08-11 |