Issued Patents All Time
Showing 1–25 of 31 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6633468 | High voltage protection circuit for improved oxide reliability | Charvaka Duvvury | 2003-10-14 |
| 6535368 | Shared 5 volt tolerant ESD protection circuit for low voltage CMOS process | Roger A. Cline | 2003-03-18 |
| 6487687 | Voltage level shifter with testable cascode devices | Terence G. W. Blake, Frederick G. Wall | 2002-11-26 |
| 6445229 | Digital phase lock loop | Stephen R. Schenck | 2002-09-03 |
| 6380786 | Digital phase lock loop | Stephen R. Schenck | 2002-04-30 |
| 6353520 | Shared 5 volt tolerant ESD protection circuit for low voltage CMOS process | Roger A. Cline | 2002-03-05 |
| 6310379 | NMOS triggered NMOS ESD protection circuit using low voltage NMOS transistors | Roger A. Cline | 2001-10-30 |
| 6294943 | Method of designing fail-safe CMOS I/O buffers whose external nodes accept voltages higher than the maximum gate oxide operating voltage | Frederick G. Wall | 2001-09-25 |
| 6211693 | Testability circuit for cascode circuits used for high voltage interface | Frederick G. Wall | 2001-04-03 |
| 6147538 | CMOS triggered NMOS ESD protection circuit | Roger A. Cline | 2000-11-14 |
| 6115438 | Method and circuit for detecting a spurious lock signal from a lock detect circuit | — | 2000-09-05 |
| 6115439 | Free running digital phase lock loop | Stephen R. Schenck | 2000-09-05 |
| 6081002 | Lateral SCR structure for ESD protection in trench isolated technologies | E. Ajith Amerasekera, Amitava Chatterjee | 2000-06-27 |
| 6040708 | Output buffer having quasi-failsafe operation | Terence G. W. Blake, Frederick G. Wall | 2000-03-21 |
| 5995010 | Output buffer providing testability | Terence G. W. Blake, Frederick G. Wall | 1999-11-30 |
| 5982213 | Digital phase lock loop | Stephen R. Schenck | 1999-11-09 |
| 5844954 | Fine resolution digital delay line with coarse and fine adjustment stages | Joseph A. Casasanta, Yoshinori Satoh, Stanley C. Keeney, Robert C. Martin | 1998-12-01 |
| 5808478 | Digitally controlled output buffer to incrementally match line impedance and maintain slew rate independent of capacitive output loading | — | 1998-09-15 |
| 5802270 | Integrated circuit having an embedded digital signal processor and externally testable signal paths | Uming Ko, Glen Roy Balko, Stanley C. Keeney, Joe F. Sexton | 1998-09-01 |
| 5764077 | 5 volt tolerant I/O buffer circuit | Daniel Edmonson | 1998-06-09 |
| 5621335 | Digitally controlled output buffer to incrementally match line impedance and maintain slew rate independent of capacitive output loading | — | 1997-04-15 |
| 5544203 | Fine resolution digital delay line with coarse and fine adjustment stages | Joseph A. Casasanta, Yoshinori Satoh, Stanley C. Keeney, Robert C. Martin | 1996-08-06 |
| 5355037 | High performance digital phase locked loop | Joseph A. Casasanta, Stanley C. Keeney, Robert C. Martin, Yoshinori Satoh | 1994-10-11 |
| 5004936 | Non-loading output driver circuit | — | 1991-04-02 |
| 4612499 | Test input demultiplexing circuit | Stanley C. Keeney | 1986-09-16 |