TB

Terence G. W. Blake

TI Texas Instruments: 22 patents #515 of 12,488Top 5%
Overall (All Time): #173,583 of 4,157,543Top 5%
24
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
10081406 Quick-assembly bicycle components 2018-09-25
9889904 Quick-assembly front end for bicycles 2018-02-13
8472228 Array-based integrated circuit with reduced proximity effects Xiaowei Deng, Wah Kit Loh, Anand Seshadri 2013-06-25
8472229 Array-based integrated circuit with reduced proximity effects Xiaowei Deng, Wah Kit Loh, Anand Seshadri 2013-06-25
6980459 Non-volatile SRAM Anand Seshadri, Jarrod Eliason 2005-12-27
6487687 Voltage level shifter with testable cascode devices Bernhard H. Andresen, Frederick G. Wall 2002-11-26
6157223 Output buffer with switching PMOS drivers 2000-12-05
6040708 Output buffer having quasi-failsafe operation Bernhard H. Andresen, Frederick G. Wall 2000-03-21
5995010 Output buffer providing testability Bernhard H. Andresen, Frederick G. Wall 1999-11-30
5917212 Memory cell with capacitance for single event upset protection Theodore W. Houston 1999-06-29
5204990 Memory cell with capacitance for single event upset protection Theodore W. Houston 1993-04-20
5107139 On-chip transient event detector Theodore W. Houston, Hsindao Lu 1992-04-21
5079605 Silicon-on-insulator transistor with selectable body node to source node connection 1992-01-07
5079604 SOI layout for low resistance gate Theodore W. Houston 1992-01-07
5046044 SEU hardened memory cell Theodore W. Houston 1991-09-03
5026656 MOS transistor with improved radiation hardness Mishel Matloubian, Cheng-Eng D. Chen 1991-06-25
4974051 MOS transistor with improved radiation hardness Mishel Matloubian, Cheng-Eng D. Chen 1990-11-27
4965213 Silicon-on-insulator transistor with body node to source node connection 1990-10-23
4946799 Process for making high performance silicon-on-insulator transistor with body node to source node connection Hsindao Lu 1990-08-07
4914629 Memory cell including single event upset rate reduction circuitry Theodore W. Houston 1990-04-03
4912675 Single event upset hardened memory cell Theodore W. Houston 1990-03-27
4906587 Making a silicon-on-insulator transistor with selectable body node to source node connection 1990-03-06
4899202 High performance silicon-on-insulator transistor with body node to source node connection Hsindao Lu 1990-02-06
4623989 Memory with p-channel cell access transistors 1986-11-18