Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11455452 | Variable implant and wafer-level feed-forward for dopant dose optimization | Mahalingam Nandakumar, Murlidhar Bashyam, Douglas Newman | 2022-09-27 |
| 9431248 | High tilt angle plus twist drain extension implant for CHC lifetime improvement | Xiang-Zheng Bo, Douglas T. Grider | 2016-08-30 |
| 9397164 | Deep collector vertical bipolar transistor with enhanced gain | Brian Edward Hornung, Xiang-Zheng Bo, Amitava Chatterjee | 2016-07-19 |
| 9379176 | Well resistors and polysilicon resistors | Stephen Keith Heinrich-Barna, Douglas P. Verret | 2016-06-28 |
| 9245755 | Deep collector vertical bipolar transistor with enhanced gain | Brian Edward Hornung, Xiang-Zheng Bo, Amitava Chatterjee | 2016-01-26 |
| 9202859 | Well resistors and polysilicon resistors | Stephen Keith Heinrich-Barna, Douglas P. Verret | 2015-12-01 |
| 9177802 | High tilt angle plus twist drain extension implant for CHC lifetime improvement | Xiang-Zheng Bo, Douglas T. Grider | 2015-11-03 |
| 8753938 | Method for 1/F noise reduction in NMOS devices | Purushothaman Srinivasan | 2014-06-17 |
| 8653607 | Method for 1/F noise reduction in NMOS devices | Purushothaman Srinivasan | 2014-02-18 |
| 8067279 | Application of different isolation schemes for logic and embedded memory | Kayvan Sadra, Seetharaman Sridhar, Amitava Chatterjee | 2011-11-29 |
| 7662688 | Application of different isolation schemes for logic and embedded memory | Kayvan Sadra, Seetharaman Sridhar, Amitava Chatterjee | 2010-02-16 |
| 7314800 | Application of different isolation schemes for logic and embedded memory | Kayvan Sadra, Seetharaman Sridhar, Amitava Chatterjee | 2008-01-01 |
| 7274046 | Tri-gate low power device and method for manufacturing the same | Lahir Shaik Adam, Eddie Hearl Breashears | 2007-09-25 |
| 7250334 | Metal insulator metal (MIM) capacitor fabrication with sidewall spacers and aluminum cap (ALCAP) top electrode | Darius Crenshaw, Byron Lovell Williams, Hisashi Shichijo, Satyavolu S. Papa Rao, Kenneth D. Brennan +1 more | 2007-07-31 |
| 7199011 | Method to reduce transistor gate to source/drain overlap capacitance by incorporation of carbon | Majid Mansoori, Antonio Luis Pacheco Rotondaro, Brian Smith | 2007-04-03 |
| 7193277 | Application of different isolation schemes for logic and embedded memory | Kayvan Sadra, Seetharaman Sridhar, Amitava Chatterjee | 2007-03-20 |
| 7141468 | Application of different isolation schemes for logic and embedded memory | Kayvan Sadra, Seetharaman Sridhar, Amitava Chatterjee | 2006-11-28 |
| 7141480 | Tri-gate low power device and method for manufacturing the same | Lahir Shaik Adam, Eddie Hearl Breashears | 2006-11-28 |
| 7045436 | Method to engineer the inverse narrow width effect (INWE) in CMOS technology using shallow trench isolation (STI) | Amitava Chatterjee, Manuel Quevedo-Lopez, Jong Shik Yoon, Shaoping Tang | 2006-05-16 |
| 6693357 | Methods and semiconductor devices with wiring layer fill structures to improve planarization uniformity | Christopher Lyle Borst, Bobby David Strong, Noel Russell | 2004-02-17 |
| 6333238 | Method for minimizing the temperature coefficient of resistance of passive resistors in an integrated circuit process flow | Greg Baldwin | 2001-12-25 |
| 6211769 | System to minimize the temperature coefficient of resistance of passive resistors in an integrated circuit process flow | Greg Baldwin | 2001-04-03 |
| 6162728 | Method to optimize copper chemical-mechanical polishing in a copper damascene interconnect process for integrated circuit applications | Paul Gillespie | 2000-12-19 |
| 6143594 | On-chip ESD protection in dual voltage CMOS | Vikas Gupta, Gregory Charles Baldwin, E. Ajith Amerasekera, David B. Spratt, Timothy A. Rost | 2000-11-07 |
| 6137144 | On-chip ESD protection in dual voltage CMOS | Vikas Gupta, Gregory Charles Baldwin, E. Ajith Amerasekera, David B. Spratt, Timothy A. Rost | 2000-10-24 |