Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11670386 | Method for suppressing gate oxide tunnel current in non-volatile memory to reduce disturbs | Clyde F. Dunn, Aswin N. Mehta, John Howard MacPeak | 2023-06-06 |
| 10593413 | Memory circuit with leakage compensation | Raviprakash Suryanarayana Rao | 2020-03-17 |
| 10535409 | Method for suppressing gate oxide tunnel current in non-volatile memory to reduce disturbs | Clyde F. Dunn, Aswin N. Mehta, John Howard MacPeak | 2020-01-14 |
| 10504567 | Sense amplifier with offset compensation | Robert Antonio Glazewski, Saim Ahmad Qidwai | 2019-12-10 |
| 10199078 | Sense amplifier with offset compensation | Robert Antonio Glazewski, Saim Ahmad Qidwai | 2019-02-05 |
| 10062443 | Memory circuit with leakage compensation | Raviprakash Suryanarayana Rao | 2018-08-28 |
| 9799408 | Memory circuit with leakage compensation | Raviprakash Suryanarayana Rao | 2017-10-24 |
| 9711715 | Method of manufacturing a dual mode ferroelectric random access memory (FRAM) having imprinted read-only (RO) data | Chiraag Juvekar, Joyce Kwong, Clive Bittlestone, Srinath Ramaswamy | 2017-07-18 |
| 9704554 | Sense amplifier with offset compensation | Robert Antoni Glazewski, Saim Ahmad Qidwai | 2017-07-11 |
| 9401196 | Dual mode ferroelectric random access memory (FRAM) cell apparatus and methods with imprinted read-only (RO) data | Chiraag Juvekar, Joyce Kwong, Clive Bittlestone, Srinath Ramaswamy | 2016-07-26 |
| 9379176 | Well resistors and polysilicon resistors | Douglas P. Verret, Alwin Tsao | 2016-06-28 |
| 9236107 | FRAM cell with cross point access | Saim Ahmad Qidwai, William F. Kraus | 2016-01-12 |
| 9202859 | Well resistors and polysilicon resistors | Douglas P. Verret, Alwin Tsao | 2015-12-01 |
| 7813198 | System and method for reading memory | Sung-Wei Lin | 2010-10-12 |
| 7379354 | Methods and apparatus to provide voltage control for SRAM write assist circuits | Jonathon Miller | 2008-05-27 |
| 6646925 | Method and system for discharging the bit lines of a memory cell array after erase operation | Cetin Kaya | 2003-11-11 |