Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8134204 | DEMOS transistors with STI and compensated well in drain | Kamel Benaissa | 2012-03-13 |
| 7915905 | Process and temperature insensitive flicker noise monitor circuit | Baher Haroun, Gaurav Chandra, Vijaya B. Rentala, Venkatesh Srinivasan, Krishnaswamy Nagaraj | 2011-03-29 |
| 7719299 | Process and temperature insensitive flicker noise monitor circuit | Baher Haroun, Gaurav Chandra, Vijaya B. Rentala, Venkatesh Srinivasan, Krishnaswamy Nagaraj | 2010-05-18 |
| 7692217 | Matched analog CMOS transistors with extension wells | Henry Litzmann Edwards, Tathagata Chatterjee, Shyh-Horng Yang, Lance Robertson | 2010-04-06 |
| 7250334 | Metal insulator metal (MIM) capacitor fabrication with sidewall spacers and aluminum cap (ALCAP) top electrode | Darius Crenshaw, Byron Lovell Williams, Alwin Tsao, Satyavolu S. Papa Rao, Kenneth D. Brennan +1 more | 2007-07-31 |
| 6764892 | Device and method of low voltage SCR protection for high voltage failsafe ESD applications | Keith E. Kunz, Charvaka Duvvury | 2004-07-20 |
| 6753202 | CMOS photodiode having reduced dark current and improved light sensitivity and responsivity | Zhiliang Chen, Kuok Ling, Katsuo Komatsuzaki, Chin-Yu Tsai | 2004-06-22 |
| 6621064 | CMOS photodiode having reduced dark current and improved light sensitivity and responsivity | Zhiliang Chen, Kuok Ling, Katsuo Komatsuzaki, Chin-Yu Tsai | 2003-09-16 |
| 6576959 | Device and method of low voltage SCR protection for high voltage failsafe ESD applications | Keith E. Kunz, Charvaka Duvvury | 2003-06-10 |
| 6512280 | Integrated CMOS structure for gate-controlled buried photodiode | Zhiliang Chen, Kuok Ling, Katsuo Komatsuzaki, Chin-Yu Tsai | 2003-01-28 |
| 6392263 | Integrated structure for reduced leakage and improved fill-factor in CMOS pixel | Zhiliang Chen, Kuok Ling, Katsuo Komatsuzaki, Chin-Yu Tsai | 2002-05-21 |
| 6303420 | Integrated bipolar junction transistor for mixed signal circuits | Seetharaman Sridhar, Amitava Chatterjee, Alec J. Morton | 2001-10-16 |
| 5959308 | Epitaxial layer on a heterointerface | Richard J. Matyi | 1999-09-28 |
| 5894145 | Multiple substrate bias random access memory device | Ih-Chin Chen, Clarence W. Teng | 1999-04-13 |
| 5595925 | Method for fabricating a multiple well structure for providing multiple substrate bias for DRAM device formed therein | Ih-Chin Chen, Clarence W. Teng | 1997-01-21 |
| 5290719 | Method of making complementary heterostructure field effect transistors | Han-Tzong Yuan, Hung-Dah Shih | 1994-03-01 |
| 5238869 | Method of forming an epitaxial layer on a heterointerface | Richard J. Matyi | 1993-08-24 |
| 5214298 | Complementary heterostructure field effect transistors | Han-Tzong Yuan, Hung-Dah Shih | 1993-05-25 |
| 5164917 | Vertical one-transistor DRAM with enhanced capacitance and process for fabricating | — | 1992-11-17 |
| 5065132 | Programmable resistor and an array of the same | Albert H. Taddiken, Han-Tzong Yuan | 1991-11-12 |
| 4914053 | Heteroepitaxial selective-area growth through insulator windows | Richard J. Matyi | 1990-04-03 |
| 4910164 | Method of making planarized heterostructures using selective epitaxial growth | — | 1990-03-20 |
| 4713678 | dRAM cell and method | Richard Womack, Sanjay Banerjee, Satwinder S. Malhi | 1987-12-15 |
| 4545034 | Contactless tite RAM | Pallab K. Chatterjee, John E. Leiss | 1985-10-01 |