Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12338549 | Method and system for liquid encapsulated growth of cadmium zinc telluride crystals | Luigi Colombo, Victor Perez-Rubio, Tim Svoboda, Fred Harris, Kathryn M. O'Brien | 2025-06-24 |
| 11866848 | Method and system for liquid encapsulated growth of cadmium zinc telluride crystals | Luigi Colombo, Victor Perez-Rubio, Tim Svoboda, Fred Harris, Kathryn M. O'Brien | 2024-01-09 |
| 7807978 | Divergent charged particle implantation for improved transistor symmetry | James D. Bernstein, Said Ghneim, Jiejie Xu, Jeffrey Loewecke | 2010-10-05 |
| 7692217 | Matched analog CMOS transistors with extension wells | Henry Litzmann Edwards, Hisashi Shichijo, Tathagata Chatterjee, Shyh-Horng Yang | 2010-04-06 |
| 7638415 | Method for reducing dislocation threading using a suppression implant | Martin B. Mollat, Tathagata Chatterjee, Henry Litzmann Edwards, Richard B. Irwin, Binghua Hu | 2009-12-29 |
| 7466009 | Method for reducing dislocation threading using a suppression implant | Martin B. Mollat, Tathagata Chatterjee, Henry Litzmann Edwards, Richard B. Irwin, Binghua Hu | 2008-12-16 |
| 7422967 | Method for manufacturing a semiconductor device containing metal silicide regions | Juanita DeLoach, Lindsey Hall, Jiong-Ping Lu, Donald Miles | 2008-09-09 |
| 7385202 | Divergent charged particle implantation for improved transistor symmetry | James D. Bernstein, Said Ghneim, Jiejie Xu, Jeffrey Loewecke | 2008-06-10 |
| 7335595 | Silicide formation using a low temperature anneal process | Jiong-Ping Lu, Donald Miles | 2008-02-26 |
| 7253072 | Implant optimization scheme | James D. Bernstein, Said Ghneim, Nandu Mahalingam, Benjamin G. Moser | 2007-08-07 |
| 7232744 | Method for implanting dopants within a substrate by tilting the substrate relative to the implant source | Said Ghneim, James D. Bernstein, Jiejie Xu, Jeffrey Loewecke | 2007-06-19 |
| 7208409 | Integrated circuit metal silicide method | Jiong-Ping Lu, Duofeng Yue, Xiaozhan Liu, Donald Miles | 2007-04-24 |
| 7033879 | Semiconductor device having optimized shallow junction geometries and method for fabrication thereof | Brian Edward Hornung, Xin Zhang, Srinivasan Chakravarthi, Beriannan Chidambaram | 2006-04-25 |
| 7029967 | Silicide method for CMOS integrated circuits | Song Zhao, Sue Crank, Amitava Chatterjee, Kaiping Liu, Jiong-Ping Lu +2 more | 2006-04-18 |
| 6699771 | Process for optimizing junctions formed by solid phase epitaxy | — | 2004-03-02 |