Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9048180 | Low stress sacrificial cap layer | Jiong-Ping Lu, Periannan Chidambaram | 2015-06-02 |
| 8084312 | Nitrogen based implants for defect reduction in strained silicon | P R Chidambaram, Rajesh Khamankar, Haowen Bu, Douglas T. Grider | 2011-12-27 |
| 7994073 | Low stress sacrificial cap layer | Jiong-Ping Lu, Periannan Chidambaram | 2011-08-09 |
| 7902576 | Phosphorus activated NMOS using SiC process | P.R. Chidambaram | 2011-03-08 |
| 7795122 | Antimony ion implantation for semiconductor components | Haowen Bu, Amitabh Jain, Shashank S. Ekbote | 2010-09-14 |
| 7786518 | Growth of unfaceted SiGe in MOS transistor fabrication | Periannan Chidambaram | 2010-08-31 |
| 7670892 | Nitrogen based implants for defect reduction in strained silicon | PR Chidambaram, Rajesh Khamankar, Haowen Bu, Douglas T. Grider | 2010-03-02 |
| 7572716 | Semiconductor doping with improved activation | Haowen Bu, Shashank S. Ekbote, Borna J. Obradovic | 2009-08-11 |
| 7553717 | Recess etch for epitaxial SiGe | Periannan Chidambaram, Johan W. Weijtmans | 2009-06-30 |
| 7371648 | Method for manufacturing a transistor device having an improved breakdown voltage and a method for manufacturing an integrated circuit using the same | Jihong Chen, Eddie Hearl Breashears, Amitabh Jain | 2008-05-13 |
| 7208380 | Interface improvement by stress application during oxide growth through use of backside films | Anand Krishnan, Haowen Bu | 2007-04-24 |
| 7179696 | Phosphorus activated NMOS using SiC process | Periannan Chidambaram | 2007-02-20 |
| 7129127 | Integration scheme to improve NMOS with poly cap while mitigating PMOS degradation | Periannan Chidambaram, Haowen Bu, Rajesh Khamankar | 2006-10-31 |
| 7118977 | System and method for improved dopant profiles in CMOS transistors | PR Chidambaram | 2006-10-10 |
| 7112516 | Fabrication of abrupt ultra-shallow junctions | Periannan Chidambaram | 2006-09-26 |
| 7061058 | Forming a retrograde well in a transistor to enhance performance of the transistor | PR Chidambaram, Robert C. Bowen, Haowen Bu | 2006-06-13 |
| 7033879 | Semiconductor device having optimized shallow junction geometries and method for fabrication thereof | Brian Edward Hornung, Xin Zhang, Lance Robertson, Beriannan Chidambaram | 2006-04-25 |
| 6927137 | Forming a retrograde well in a transistor to enhance performance of the transistor | PR Chidambaram, Robert C. Bowen, Haowen Bu | 2005-08-09 |
| 6852603 | Fabrication of abrupt ultra-shallow junctions | Periannan Chidambaram | 2005-02-08 |
| 6849528 | Fabrication of ultra shallow junctions from a solid source with fluorine implantation | Periannan Chidambaram | 2005-02-01 |
| 6847089 | Gate edge diode leakage reduction | Suresh Potla, Gordon P. Pollack, Amitabh Jain | 2005-01-25 |
| 6830980 | Semiconductor device fabrication methods for inhibiting carbon out-diffusion in wafers having carbon-containing regions | Majid Mansoori, Donald Miles, P R Chidambaram | 2004-12-14 |
| 6797593 | Methods and apparatus for improved mosfet drain extension activation | Amitabh Jain, Xin Zhang | 2004-09-28 |
| 6682980 | Fabrication of abrupt ultra-shallow junctions using angled PAI and fluorine implant | P.R. Chidambaram, Amitava Chatterjee | 2004-01-27 |