GP

Gordon P. Pollack

TI Texas Instruments: 17 patents #768 of 12,488Top 7%
Overall (All Time): #278,895 of 4,157,543Top 7%
17
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
7479668 Source/drain extension implant process for use with short time anneals Amitabh Jain 2009-01-20
7297605 Source/drain extension implant process for use with short time anneals Amitabh Jain 2007-11-20
6847089 Gate edge diode leakage reduction Srinivasan Chakravarthi, Suresh Potla, Amitabh Jain 2005-01-25
5482871 Method for forming a mesa-isolated SOI transistor having a split-process polysilicon gate 1996-01-09
5240512 Method and structure for forming a trench within a semiconductor layer of material 1993-08-31
5225697 dRAM cell and method Satwinder S. Malhi, William F. Richardson 1993-07-06
5185280 Method of fabricating a SOI transistor with pocket implant and body-to-source (BTS) contact Theodore W. Houston 1993-02-09
5162882 Semiconductor over insulator mesa 1992-11-10
5120675 Method for forming a trench within a semiconductor layer of material 1992-06-09
5039621 Semiconductor over insulator mesa and method of forming the same 1991-08-13
4956307 Thin oxide sidewall insulators for silicon-over-insulator transistors Mishel Matloubian, Ravishankar Sundaresan 1990-09-11
4939104 Method for forming a buried lateral contact Donald M. Bordelon, William F. Richardson, Satwinder S. Malhi 1990-07-03
4797373 Method of making dRAM cell with trench capacitor Satwinder S. Malhi 1989-01-10
4659426 Plasma etching of refractory metals and their silicides Clyde R. Fuller, Robert H. Eklund, Dave Monahan 1987-04-21
4580330 Integrated circuit isolation Clarence W. Teng, William R. Hunter, Christopher Slawinski, Robert Reid Doering 1986-04-08
4541167 Method for integrated circuit device isolation Robert H. Havemann 1985-09-17
4538343 Channel stop isolation technology utilizing two-step etching and selective oxidation with sidewall masking Clarence W. Teng, William R. Hunter 1985-09-03