Issued Patents All Time
Showing 25 most recent of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11996343 | Thermal routing trench by additive processing | Benjamin Stassen Cook, Archana Venugopal, Luigi Colombo | 2024-05-28 |
| 11676880 | High thermal conductivity vias by additive processing | Benjamin Stassen Cook, Archana Venugopal, Luigi Colombo | 2023-06-13 |
| 11004680 | Semiconductor device package thermal conduit | Archana Venugopal, Benjamin Stassen Cook, Luigi Colombo | 2021-05-11 |
| 10861763 | Thermal routing trench by additive processing | Benjamin Stassen Cook, Archana Venugopal, Luigi Colombo | 2020-12-08 |
| 10811334 | Integrated circuit nanoparticle thermal routing structure in interconnect region | Benjamin Stassen Cook, Archana Venugopal, Luigi Colombo | 2020-10-20 |
| 10790228 | Interconnect via with grown graphitic material | Archana Venugopal, Benjamin Stassen Cook, Luigi Colombo | 2020-09-29 |
| 10529641 | Integrated circuit nanoparticle thermal routing structure over interconnect region | Archana Venugopal, Benjamin Stassen Cook, Luigi Colombo | 2020-01-07 |
| 10256188 | Interconnect via with grown graphitic material | Archana Venugopal, Benjamin Stassen Cook, Luigi Colombo | 2019-04-09 |
| 10181521 | Graphene heterolayers for electronic applications | Archana Venugopal, Benjamin Stassen Cook, Luigi Colombo | 2019-01-15 |
| 10069065 | Low noise graphene hall sensors, systems and methods of making and using same | Arup Polley, Archana Venugopal, Luigi Colombo | 2018-09-04 |
| 10001529 | Low-offset Graphene Hall sensor | Arup Polley, Archana Venugopal, Luigi Colombo | 2018-06-19 |
| 9793214 | Heterostructure interconnects for high frequency applications | Archana Venugopal, Benjamin Stassen Cook, Luigi Colombo | 2017-10-17 |
| 9517938 | Applying spatial gradient magnetic field to metallic/semiconducting SWNTs in fluid | James Cooper Wainerdi, Luigi Colombo | 2016-12-13 |
| 9114995 | Separating Metallic and Semiconductor SWNTS with sinusoidal dipole-inducing magnetic fields | James Cooper Wainerdi, Luigi Colombo | 2015-08-25 |
| 8789705 | Separating metallic and semiconductor SWNTs with varying dipole-inducing magnetic fields | James Cooper Wainerdi, Luigi Colombo | 2014-07-29 |
| 8753924 | Grown carbon nanotube die attach structures, articles, devices, and processes for making them | James Cooper Wainerdi, Luigi Colombo, John Paul Tellkamp | 2014-06-17 |
| 6990035 | Circuit and method for reducing SRAM standby power | Donald J. Redwine | 2006-01-24 |
| 5374580 | Method of forming high density DRAM having increased capacitance area due to trench etched into storage capacitor region | David A. Baglee, Gregory J. Armstrong | 1994-12-20 |
| 5334548 | High performance composed pillar dRAM cell | Bing W. Shen, William F. Richardson | 1994-08-02 |
| 5300450 | High performance composed pillar DRAM cell | Bing W. Shen, William F. Richardson | 1994-04-05 |
| 5198383 | Method of fabricating a composed pillar transistor DRAM Cell | Clarence W. Teng | 1993-03-30 |
| 5170234 | High density dynamic RAM with trench capacitor | David A. Baglee, Gregory J. Armstrong | 1992-12-08 |
| 5156992 | Process for forming poly-sheet pillar transistor DRAM cell | Clarence W. Teng | 1992-10-20 |
| 5106776 | Method of making high performance composed pillar dRAM cell | Bing W. Shen, William F. Richardson | 1992-04-21 |
| 5103276 | High performance composed pillar dRAM cell | Bing W. Shen, William F. Richardson | 1992-04-07 |