Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11024620 | Integrated circuits and processes for protection of standard cell performance from context effects | Thomas J. Aton, Roger Mark Terry | 2021-06-01 |
| 10192859 | Integrated circuits and processes for protection of standard cell performance from context effects | Thomas J. Aton, Roger Mark Terry | 2019-01-29 |
| 9001570 | Pseudo retention till access mode enabled memory | Rashmi Sachan, Parvinder Kumar Rana, Abhishek Kesarwani | 2015-04-07 |
| 8595656 | Marker layer to facilitate mask build with interactive layers | Thomas J. Aton, Gregory Charles Baldwin | 2013-11-26 |
| 8344479 | Integrated circuit inductor with integrated vias | Greg Baldwin | 2013-01-01 |
| 8093716 | Contact fuse which does not touch a metal layer | Bryan Sheffield, Roger Griesmer, Joe W. McPherson | 2012-01-10 |
| 7961546 | Memory power management systems and methods | Hugh Mair, Alice Wang, Sumanth K. Gururjarao, Ramaprasath Vilangudipitchai, Gordon Gammie +1 more | 2011-06-14 |
| 7888227 | Integrated circuit inductor with integrated vias | Greg Baldwin | 2011-02-15 |
| 7800409 | Logic block, a multi-track standard cell library, a method of designing a logic block and an asic employing the logic block | — | 2010-09-21 |
| 7784015 | Method for generating a mask layout and constructing an integrated circuit | — | 2010-08-24 |
| 7671663 | Tunable voltage controller for a sub-circuit and method of operating the same | Theodore W. Houston, Michael Patrick Clinton | 2010-03-02 |
| 7400025 | Integrated circuit inductor with integrated vias | Greg Baldwin | 2008-07-15 |
| 6933731 | Method and system for determining transistor degradation mechanisms | Vijay Reddy | 2005-08-23 |
| 6876594 | Integrated circuit with programmable fuse array | Roger Griesmer, Bryan Sheffield, Kun-His Li, Mark Jensen, Vinod Menezes | 2005-04-05 |
| 6747481 | Adaptive algorithm for electrical fuse programming | — | 2004-06-08 |
| 6735146 | System and method for pulling electrically isolated memory cells in a memory array to a non-floating state | David J. Toops | 2004-05-11 |
| 6614703 | Method and system for configuring integrated systems on a chip | Baher Haroun | 2003-09-02 |
| 6608792 | Method and apparatus for storing data in an integrated circuit | — | 2003-08-19 |
| 6567323 | Memory circuit redundancy control | Clayton O. Timmons | 2003-05-20 |
| 6449193 | Burst access memory system | Andrew M. Love | 2002-09-10 |
| 6381175 | Method and system for validating flash memory | — | 2002-04-30 |
| 6292422 | Read/write protected electrical fuse | — | 2001-09-18 |
| 6052308 | Balanced sensing arrangement for flash EEPROM | — | 2000-04-18 |
| 5160774 | Scorch prevention device | — | 1992-11-03 |
| 4894166 | Method for cleaning oil-contaminated water in a swimming or bathing area | — | 1990-01-16 |