Issued Patents All Time
Showing 25 most recent of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10867681 | SRAM memory having subarrays with common IO block | Michael Patrick Clinton, Marty Tsai, Rajinder Paul Singh | 2020-12-15 |
| 9419617 | Circuit for reducing negative bias temperature instability | Chan-Hong Chern, Fu-Lung Hsueh, Ming-Chieh Huang, Chih-Chang Lin | 2016-08-16 |
| 8791720 | Circuit for reducing negative bias temperature instability | Chan-Hong Chern, Fu-Lung Hsueh, Ming-Chieh Huang, Chih-Chang Lin | 2014-07-29 |
| 8570068 | Circuit for reducing negative bias temperature instability | Chan-Hong Chern, Fu-Lung Hsueh, Ming-Chieh Huang, Chih-Chang Lin | 2013-10-29 |
| 8522174 | Semiconductor memory | — | 2013-08-27 |
| 8331187 | Memory with low power mode for write | Theodore W. Houston, Michael Patrick Clinton | 2012-12-11 |
| 8093716 | Contact fuse which does not touch a metal layer | Robert L. Pitts, Roger Griesmer, Joe W. McPherson | 2012-01-10 |
| 7512030 | Memory with low power mode for WRITE | Theodore W. Houston, Michael Patrick Clinton | 2009-03-31 |
| 7471536 | Match mismatch emulation scheme for an addressed location in a CAM | Rengarajan S. Krishnan, Rashmi Sachan, Nisha Padattil Kuliyampattil | 2008-12-30 |
| 7466576 | Technique for CAM width expansion using an external priority encoder | Santhosh Narayanaswamy, Robert J. Landers | 2008-12-16 |
| 7376871 | CAM test structures and methods therefor | George E. Harris, Dwayne Ward | 2008-05-20 |
| 7349285 | Dual port memory unit using a single port memory core | Suresh Balasubramanian, Lakshmikantha V. Holla | 2008-03-25 |
| 7301849 | System for reducing row periphery power consumption in memory devices | Xiaowei Deng, Theodore W. Houston | 2007-11-27 |
| 7274581 | Array fault testing approach for TCAMs | Theo J. Powell, Rashmi Sachan | 2007-09-25 |
| 7234034 | Self-clocking memory device | Stephen Wayne Spriggs, Vikas Agrawal, Eric Louis Pierre Badi | 2007-06-19 |
| 7230868 | Stable source-coupled sense amplifier | Sudhir K. Madan | 2007-06-12 |
| 7200730 | Method of operating a memory at high speed using a cycle ready status output signal | Vikas Agrawal, Stephen Wayne Spriggs, Eric Louis Pierre Badi | 2007-04-03 |
| 7170769 | High performance and reduced area architecture for a fully parallel search of a TCAM cell | Rashmi Sachan, Santhosh Narayanaswamy, George B. Jamison | 2007-01-30 |
| 7120082 | System for reducing row periphery power consumption in memory devices | Xiaowei Deng, Theodore W. Houston | 2006-10-10 |
| 7095671 | Electrical fuse control of memory slowdown | Manjeri Krishnan, Joel J. Graber, Duy-Loan T. Le, Sanjive Agarwala | 2006-08-22 |
| 7016245 | Tracking circuit enabling quick/accurate retrieval of data stored in a memory array | Suresh Balasubramanian, Stephen Wayne Spriggs, Mohan Mishra | 2006-03-21 |
| 7012846 | Sense amplifier for a memory array | Suresh Balasubramanian, Stephen Wayne Spriggs, Mohan Mishra | 2006-03-14 |
| 6956789 | Cycle ready circuit for self-clocking memory device | Vikas Agrawal, Stephen Wayne Spriggs | 2005-10-18 |
| 6928011 | Electrical fuse control of memory slowdown | Manjeri Krishnan, Joel J. Graber, Duy-Loan T. Le, Sanjive Agarwala | 2005-08-09 |
| 6909301 | Oscillation based access time measurement | Steven Korson, Brian D. Borchers, Clive Bittlestone, Doug Counce | 2005-06-21 |