Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9692446 | Delta-Sigma ADC with wait-for-sync feature | — | 2017-06-27 |
| 8549338 | Low-power data loop recorder | Suribhotla Rajasekhar | 2013-10-01 |
| 8423837 | High reliability and low power redundancy for memory | Sudhir K. Madan, David J. Toops | 2013-04-16 |
| 7466576 | Technique for CAM width expansion using an external priority encoder | Santhosh Narayanaswamy, Bryan Sheffield | 2008-12-16 |
| 6930953 | Self-timed strobe generator and method for use with multi-strobe random access memories to increase memory bandwidth | Keerthinarayan P. Heragu, Mustafa Ulvi Erdogan | 2005-08-16 |
| 5789956 | Low power flip-flop | Shivaling S. Mahant-Shetti | 1998-08-04 |
| 5751162 | Field programmable gate array logic module configurable as combinational or sequential circuits | Mahesh M. Mehendale, Shivaling S. Mahant-Shetti, Manisha Agarwala, Mark G. Harward | 1998-05-12 |
| 5654981 | Signal transmission system and method of operation | Shivaling S. Mahant-Shetti | 1997-08-05 |
| 5612632 | High speed flip-flop for gate array | Shivaling S. Mahant-Shetti, Kevin M. Ovens, Clive Bittlestone, Robert C. Martin | 1997-03-18 |
| 5535241 | Signal transmission system and method of operation | Shivaling S. Mahant-Shetti | 1996-07-09 |
| 5502404 | Gate array cell with predefined connection patterns | Shivaling S. Mahant-Shetti, R. Krishman, C. Mutukrishnan | 1996-03-26 |
| 5488315 | Adder-based base cell for field programmable gate arrays | Shivaling S. Mahant-Shetti, Manisha Agarwala, Mahesh M. Mehendale, Mark G. Harward | 1996-01-30 |
| 5469079 | Flip-flop for use in LSSD gate arrays | Shivaling S. Mahant-Shetti | 1995-11-21 |
| 5428304 | Programmable gate array with special interconnects for adjacent gates and isolation devices used during programming | Mark G. Harward, Jeffrey A. Niehaus, Daniel Edmonson | 1995-06-27 |
| 5422581 | Gate array cell with predefined connection patterns | Shivaling S. Mahant-Shetti | 1995-06-06 |
| 5391943 | Gate array cell with predefined connection patterns | Shivaling S. Mahant-Shetti | 1995-02-21 |