TP

Theo J. Powell

TI Texas Instruments: 21 patents #558 of 12,488Top 5%
Overall (All Time): #211,302 of 4,157,543Top 6%
21
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
7328388 Built-in self-test arrangement for integrated circuit memory devices Kuong Hua Hii, Danny R. Cline 2008-02-05
7278078 Built-in self-test arrangement for integrated circuit memory devices Kuong Hua Hii, Danny R. Cline 2007-10-02
7274581 Array fault testing approach for TCAMs Bryan Sheffield, Rashmi Sachan 2007-09-25
6801461 Built-in self-test arrangement for integrated circuit memory devices Kuong Hua Hii, Danny R. Cline 2004-10-05
6353563 Built-in self-test arrangement for integrated circuit memory devices Kuong Hua Hii, Danny R. Cline 2002-03-05
6014336 Test enable control for built-in self-test Kuong Hua Hii, Danny R. Cline 2000-01-11
5959912 ROM embedded mask release number for built-in self-test Kuong Hua Hii, Danny R. Cline, Wah Kit Loh 1999-09-28
5953272 Data invert jump instruction test for built-in self-test Kuong Hua Hii, Danny R. Cline 1999-09-14
5936900 Integrated circuit memory device having built-in self test circuit with monitor and tester modes Kuong Hua Hii, Daniel R. Cline 1999-08-10
5923599 Apparatus and method for subarray testing in dynamic random access memories using a built-in-self-test unit Kuong Hua Hii, Danny R. Cline, Wah Kit Loh 1999-07-13
5883843 Built-in self-test arrangement for integrated circuit memory devices Kuong Hua Hii, Danny R. Cline 1999-03-16
5875153 Internal/external clock option for built-in self test Kuong Hua Hii, Danny R. Cline 1999-02-23
5694402 System and method for structurally testing integrated circuit devices Kenneth M. Butler 1997-12-02
5032783 Test circuit and scan tested logic device with isolated data lines during testing Yin-Chao Hwang 1991-07-16
5012471 Value-strength based test pattern generator and process John I. Hickman, Jeri J. Crowley 1991-04-30
4870346 Distributed pseudo random sequence control with universal polynomial function generator for LSI/VLSI test systems Marc R. Mydill 1989-09-26
4710931 Partitioned scan-testing system Jeffrey D. Bellay 1987-12-01
4710933 Parallel/serial scan system for testing logic circuits Jeffrey D. Bellay, Martin D. Daniels, Yin-Chao Hwang 1987-12-01
4701921 Modularized scan path for serially tested logic circuit Yin-Chao Hwang 1987-10-20
4698588 Transparent shift register latch for isolating peripheral ports during scan testing of a logic circuit Yin-Chao Hwang 1987-10-06
4597080 Architecture and method for testing VLSI processors Satish M. Thatte, Thirumalai Sridhar, David Ho, Han-Tzong Yuan 1986-06-24