Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6760866 | Process of operating a processor with domains and clocks | Gary L. Swoboda | 2004-07-06 |
| 6704895 | Integrated circuit with emulation register in JTAG JAP | Gary L. Swoboda, Joseph A. Coomes | 2004-03-09 |
| 6539497 | IC with selectively applied functional and test clocks | Gary L. Swoboda | 2003-03-25 |
| 6522985 | Emulation devices, systems and methods utilizing state machines | Gary L. Swoboda, Joseph A. Coomes | 2003-02-18 |
| 6349392 | Devices, systems and methods for mode driven stops | Gary L. Swoboda | 2002-02-19 |
| 6085336 | Data processing devices, systems and methods with mode driven stops | Gary L. Swoboda | 2000-07-04 |
| 5329471 | Emulation devices, systems and methods utilizing state machines | Gary L. Swoboda, Joseph A. Coomes | 1994-07-12 |
| 5173904 | Logic circuits systems, and methods having individually testable logic modules | Derek Roskell | 1992-12-22 |
| 4860290 | Logic circuit having individually testable logic modules | Derek Roskell | 1989-08-22 |
| 4710933 | Parallel/serial scan system for testing logic circuits | Theo J. Powell, Jeffrey D. Bellay, Yin-Chao Hwang | 1987-12-01 |
| 4667339 | Level sensitive latch stage | Graham S. Tubbs, Robert Schaaf, Ronald Gene Walther | 1987-05-19 |