Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7882454 | Apparatus and method for improved test controllability and observability of random resistant logic | Mary P. Kusko, Haoxing Ren, Rona Yaari | 2011-02-01 |
| 7610537 | Method and apparatus for testing multi-core microprocessors | Dan Dickinson, Robert D. Kenney, Christina Lynne Newman-LaBounty | 2009-10-27 |
| 6507929 | System and method for diagnosing and repairing errors in complementary logic | Christopher McCall Durham, Peter Juergen Klim | 2003-01-14 |
| 6253350 | Method and system for detecting errors within complementary logic circuits | Christopher McCall Durham, Peter Juergen Klim | 2001-06-26 |
| 6055658 | Apparatus and method for testing high speed components using low speed test apparatus | Talal K. Jaber, Johnny LeBlanc | 2000-04-25 |
| 5887004 | Isolated scan paths | — | 1999-03-23 |
| 5787098 | Complete chip I/O test through low contact testing using enhanced boundary scan | Sumit DasGupta, Kris V. Srikrishnan | 1998-07-28 |
| 4992732 | Method and apparatus for magnetic testing of metallic work pieces | Karl G. Walther | 1991-02-12 |
| 4888745 | Apparatus for marking individual points of an underwater construction | Karl G. Walther | 1989-12-19 |
| 4667339 | Level sensitive latch stage | Graham S. Tubbs, Martin D. Daniels, Robert Schaaf | 1987-05-19 |
| 4277699 | Latch circuit operable as a D-type edge trigger | David J. Brown, Thomas W. Williams, Michael D. Wrigglesworth | 1981-07-07 |