Patents per Year
Issued Patents All Time
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date | Approx Value ⓘ |
|---|---|---|---|---|
| 5787098 | Complete chip I/O test through low contact testing using enhanced boundary scan | Kris V. Srikrishnan, Ronald Gene Walther | 1998-07-28 | $10,920,000 |
| 4736319 | Interrupt mechanism for multiprocessing system having a plurality of interrupt lines in both a global bus and cell buses | John M. Hancock, James H. Kukula, Roger E. Peo | 1988-04-05 | $28,481,000 |
| 4509008 | Method of concurrently testing each of a plurality of interconnected integrated circuit chips | Matthew C. Graf, Robert A. Rasmussen, Thomas W. Williams | 1985-04-02 | $15,855,000 |
| 4503386 | Chip partitioning aid (CPA)-A structure for test pattern generation for large logic networks | Matthew C. Graf, Robert A. Rasmussen, Thomas W. Williams | 1985-03-05 | $15,799,000 |
| 4408336 | High speed binary counter | — | 1983-10-04 | $20,671,000 |
| 4293919 | Level sensitive scan design (LSSD) system | Prabhakar Goel, Thomas W. Williams | 1981-10-06 | $15,925,000 |