| 5787098 |
Complete chip I/O test through low contact testing using enhanced boundary scan |
Kris V. Srikrishnan, Ronald Gene Walther |
1998-07-28 |
| 4736319 |
Interrupt mechanism for multiprocessing system having a plurality of interrupt lines in both a global bus and cell buses |
John M. Hancock, James H. Kukula, Roger E. Peo |
1988-04-05 |
| 4509008 |
Method of concurrently testing each of a plurality of interconnected integrated circuit chips |
Matthew C. Graf, Robert A. Rasmussen, Thomas W. Williams |
1985-04-02 |
| 4503386 |
Chip partitioning aid (CPA)-A structure for test pattern generation for large logic networks |
Matthew C. Graf, Robert A. Rasmussen, Thomas W. Williams |
1985-03-05 |
| 4408336 |
High speed binary counter |
— |
1983-10-04 |
| 4293919 |
Level sensitive scan design (LSSD) system |
Prabhakar Goel, Thomas W. Williams |
1981-10-06 |
