Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6170078 | Fault simulation using dynamically alterable behavioral models | Mark A. Erle, Leendert M. Huisman, Zaifu Zhang | 2001-01-02 |
| 5796990 | Hierarchical fault modeling system and method | Mark A. Erle, Peter Wohl | 1998-08-18 |
| 4656580 | Logic simulation machine | Robert B. Hitchcock | 1987-04-07 |
| 4613958 | Gate array chip | Edward F. Culican, Leonard C. Ritchie | 1986-09-23 |
| 4517661 | Programmable chip tester having plural pin unit buffers which each store sufficient test data for independent operations by each pin unit | Hans P. Muhlfeld, Jr., Edward H. Valentine | 1985-05-14 |
| 4509008 | Method of concurrently testing each of a plurality of interconnected integrated circuit chips | Sumit DasGupta, Robert A. Rasmussen, Thomas W. Williams | 1985-04-02 |
| 4503386 | Chip partitioning aid (CPA)-A structure for test pattern generation for large logic networks | Sumit DasGupta, Robert A. Rasmussen, Thomas W. Williams | 1985-03-05 |