Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7900105 | Dynamically reconfigurable shared scan-in test architecture | Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux +1 more | 2011-03-01 |
| 7836368 | Dynamically reconfigurable shared scan-in test architecture | Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux +1 more | 2010-11-16 |
| 7836367 | Dynamically reconfigurable shared scan-in test architecture | Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux +1 more | 2010-11-16 |
| 7814444 | Scan compression circuit and method of design therefor | Peter Wohl, John A. Waicukauski, Sanjay Ramnath, Rohit Kapur | 2010-10-12 |
| 7774663 | Dynamically reconfigurable shared scan-in test architecture | Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux +1 more | 2010-08-10 |
| 7743299 | Dynamically reconfigurable shared scan-in test architecture | Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux +1 more | 2010-06-22 |
| 7669098 | Method and apparatus for limiting power dissipation in test | Rohit Kapur | 2010-02-23 |
| 7596733 | Dynamically reconfigurable shared scan-in test architecture | Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux +1 more | 2009-09-29 |
| 7418640 | Dynamically reconfigurable shared scan-in test architecture | Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux +1 more | 2008-08-26 |
| 6993694 | Deterministic bist architecture including MISR filter | Rohit Kapur, Tony Taylor, Peter Wohl, John A. Waicukauski | 2006-01-31 |
| 6990619 | System and method for automatically retargeting test vectors between different tester types | Rohit Kapur | 2006-01-24 |
| 6950974 | Efficient compression and application of deterministic patterns in a logic BIST architecture | Peter Wohl, John A. Waicukauski | 2005-09-27 |
| 6807646 | System and method for time slicing deterministic patterns for reseeding in logic built-in self-test | Peter Wohl, John A. Waicukauski, Rohit Kapur | 2004-10-19 |
| 6766501 | System and method for high-level test planning for layout | Suryanarayana Duggirala, Rohit Kapur | 2004-07-20 |
| 6631344 | Method and system for performing deterministic analysis and speculative analysis for more efficient automatic test pattern generation | Rohit Kapur | 2003-10-07 |
| 6615380 | Dynamic scan chains and test pattern generation methodologies therefor | Rohit Kapur, Denis Martin | 2003-09-02 |
| 6453437 | Method and system for performing transition fault simulation along long circuit paths for high-quality automatic test pattern generation | Rohit Kapur, John A. Waicukauski, Peter Wohl | 2002-09-17 |
| 6434733 | System and method for high-level test planning for layout | Suryanarayana Duggirala, Rohit Kapur | 2002-08-13 |
| 6405355 | Method for placement-based scan-in and scan-out ports selection | Suryanarayana Duggirala, Rohit Kapur | 2002-06-11 |
| 6385750 | Method and system for controlling test data volume in deterministic test pattern generation | Rohit Kapur, John A. Waicukauski, Peter Wohl | 2002-05-07 |
| 4726023 | Determination of testability of combined logic end memory by ignoring memory | John L. Carter, Leendert M. Huisman | 1988-02-16 |
| 4509008 | Method of concurrently testing each of a plurality of interconnected integrated circuit chips | Sumit DasGupta, Matthew C. Graf, Robert A. Rasmussen | 1985-04-02 |
| 4503386 | Chip partitioning aid (CPA)-A structure for test pattern generation for large logic networks | Sumit DasGupta, Matthew C. Graf, Robert A. Rasmussen | 1985-03-05 |
| 4293919 | Level sensitive scan design (LSSD) system | Sumit DasGupta, Prabhakar Goel | 1981-10-06 |
| 4277699 | Latch circuit operable as a D-type edge trigger | David J. Brown, Ronald Gene Walther, Michael D. Wrigglesworth | 1981-07-07 |