Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Determination of testability of combined logic end memory by ignoring memory

Determination of testability of combined logic end memory by ignoring memory

US Patent 4726023 · Granted Feb 16, 1988

Estimated economic value: $22,273,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Dynamically reconfigurable shared scan-in test architecture2011
Scan chain diagnostics using logic paths2011
Dynamically reconfigurable shared scan-in test architecture2010
Dynamically reconfigurable shared scan-in test architecture2010
Scan compression circuit and method of design therefor2010
Dynamically reconfigurable shared scan-in test architecture2010
Methods and apparatus for testing a scan chain to isolate defects2010
Dynamically reconfigurable shared scan-in test architecture2010
Method and apparatus for limiting power dissipation in test2010
Dynamically reconfigurable shared scan-in test architecture2009
Learning based logic diagnosis2009
Microarchitectural wire management for performance and power in partitioned arch2009