Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12333227 | Machine-learning-based design-for-test (DFT) recommendation system for improving automatic test pattern generation (ATPG) quality of results (QoR) | Apik A. Zorian, Fadi Maamari, Mahilchi Milir Vaseekar Kumar, Basim Mohammed Issa Shanyour | 2025-06-17 |
| 11829692 | Machine-learning-based design-for-test (DFT) recommendation system for improving automatic test pattern generation (ATPG) quality of results (QOR) | Apik A. Zorian, Fadi Maamari, Mahilchi Milir Vaseekar Kumar, Basim Mohammed Issa Shanyour | 2023-11-28 |
| 7900105 | Dynamically reconfigurable shared scan-in test architecture | Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux +1 more | 2011-03-01 |
| 7836368 | Dynamically reconfigurable shared scan-in test architecture | Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux +1 more | 2010-11-16 |
| 7836367 | Dynamically reconfigurable shared scan-in test architecture | Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux +1 more | 2010-11-16 |
| 7774663 | Dynamically reconfigurable shared scan-in test architecture | Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux +1 more | 2010-08-10 |
| 7743299 | Dynamically reconfigurable shared scan-in test architecture | Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux +1 more | 2010-06-22 |
| 7596733 | Dynamically reconfigurable shared scan-in test architecture | Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux +1 more | 2009-09-29 |
| 7418640 | Dynamically reconfigurable shared scan-in test architecture | Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux +1 more | 2008-08-26 |
| 6766501 | System and method for high-level test planning for layout | Rohit Kapur, Thomas W. Williams | 2004-07-20 |
| 6434733 | System and method for high-level test planning for layout | Rohit Kapur, Thomas W. Williams | 2002-08-13 |
| 6405355 | Method for placement-based scan-in and scan-out ports selection | Rohit Kapur, Thomas W. Williams | 2002-06-11 |
| 6269463 | Method and system for automatically determining transparency behavior of non-scan cells for combinational automatic test pattern generation | Harihara Ganesan, Cyrus Hay | 2001-07-31 |