Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12333227 | Machine-learning-based design-for-test (DFT) recommendation system for improving automatic test pattern generation (ATPG) quality of results (QoR) | Apik A. Zorian, Suryanarayana Duggirala, Mahilchi Milir Vaseekar Kumar, Basim Mohammed Issa Shanyour | 2025-06-17 |
| 12282063 | Scan chain formation for improving chain resolution | Emil Gizdarski | 2025-04-22 |
| 11842134 | Automated determinaton of failure mode distribution | Shivakumar Shankar Chonnad, Abhishek Chauhan, Jamileh Davoudi | 2023-12-12 |
| 11829692 | Machine-learning-based design-for-test (DFT) recommendation system for improving automatic test pattern generation (ATPG) quality of results (QOR) | Apik A. Zorian, Suryanarayana Duggirala, Mahilchi Milir Vaseekar Kumar, Basim Mohammed Issa Shanyour | 2023-11-28 |
| 11288428 | Integrated circuit design modification for localization of scan chain defects | Emil Gizdarski | 2022-03-29 |
| 8788993 | Computer system for generating an integrated and unified view of IP-cores for hierarchical analysis of a system on chip (SoC) design | Sridhar Gangadharan, Mohammad H. Movahed-Ezazi, Shaker Sarwary, Subir Chandra Ray | 2014-07-22 |
| 8533647 | Method for generating an integrated and unified view of IP-cores for hierarchical analysis of a system on chip (SoC) design | Sridhar Gangadharan, Mohammad H. Movahed-Ezazi, Shaker Sarwary, Subir Ray | 2013-09-10 |
| 7424656 | Clocking methodology for at-speed testing of scan circuits with synchronous clocks | Benoit Nadeau-Dostie, Jean-Francois Cote | 2008-09-09 |
| 7191374 | Method of and program product for performing gate-level diagnosis of failing vectors | Sonny Ngai San Shum, Benoit Nadeau-Dostie | 2007-03-13 |
| 6883134 | Method and program product for detecting bus conflict and floating bus conditions in circuit designs | Sonny Ngai San Shum | 2005-04-19 |
| 6510534 | Method and apparatus for testing high performance circuits | Benoit Nadeau-Dostie, Dwayne Burek, Jean-Francois Cote | 2003-01-21 |
| 6457161 | Method and program product for modeling circuits with latch based design | Benoit Nadeau-Dostie, Dwayne Burek | 2002-09-24 |
| 5420871 | Method for maintaining bus integrity during testing | Paul Murphy | 1995-05-30 |
| 5418792 | Method for the speedup of test vector generation for digital circuits | — | 1995-05-23 |