Issued Patents All Time
Showing 25 most recent of 48 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12046315 | Memory built-in self-test with automated reference trim feedback for memory sensing | Jongsin Yun, Martin Keim | 2024-07-23 |
| 11961576 | Method and apparatus for processing memory repair information | Luc Romain | 2024-04-16 |
| 11929136 | Reference bits test and repair using memory built-in self-test | Jongsin Yun, Harshitha Kodali | 2024-03-12 |
| 11789487 | Asynchronous interface for transporting test-related data via serial channels | Jean-Francois Cote | 2023-10-17 |
| 11495315 | Configurable built-in self-repair chain for fast repair data loading | Wei Zou | 2022-11-08 |
| 11430537 | Error-correcting code-assisted memory repair | — | 2022-08-30 |
| 8683280 | Test generator for low power built-in self-test | Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski | 2014-03-25 |
| 8516317 | Methods for at-speed testing of memory interface | Jean-Francois Cote | 2013-08-20 |
| 7757135 | Method and apparatus for storing and distributing memory repair information | Jean-Francois Cote | 2010-07-13 |
| 7617425 | Method for at-speed testing of memory interface using scan | Jean-Francois Cote | 2009-11-10 |
| 7424656 | Clocking methodology for at-speed testing of scan circuits with synchronous clocks | Jean-Francois Cote, Fadi Maamari | 2008-09-09 |
| 7370251 | Method and circuit for collecting memory failure information | Jean-Francois Cote | 2008-05-06 |
| 7257733 | Memory repair circuit and method | Saman M. I. Adham | 2007-08-14 |
| 7219282 | Boundary scan with strobed pad driver enable | Stephen K. Sunter, Pierre Gauthier | 2007-05-15 |
| 7194669 | Method and circuit for at-speed testing of scan circuits | — | 2007-03-20 |
| 7191374 | Method of and program product for performing gate-level diagnosis of failing vectors | Fadi Maamari, Sonny Ngai San Shum | 2007-03-13 |
| 7188274 | Memory repair analysis method and circuit | Robert Abbott | 2007-03-06 |
| 7155651 | Clock controller for at-speed testing of scan circuits | Jean-Francois Cote | 2006-12-26 |
| 7139946 | Method and test circuit for testing memory internal write enable | Saman M. I. Adham | 2006-11-21 |
| 6868532 | Method and program product for designing hierarchical circuit for quiescent current testing and circuit produced thereby | Jean-Francois Cote | 2005-03-15 |
| 6862717 | Method and program product for designing hierarchical circuit for quiescent current testing | Dwayne Burek | 2005-03-01 |
| 6829730 | Method of designing circuit having multiple test access ports, circuit produced thereby and method of using same | Jean-Francois Cote | 2004-12-07 |
| 6763489 | Method for scan testing of digital circuit, digital circuit for use therewith and program product for incorporating test methodology into circuit description | Jean-Francois Cote | 2004-07-13 |
| 6760874 | Test access circuit and method of accessing embedded test controllers in integrated circuit modules | Jean-Francois Cote | 2004-07-06 |
| 6745359 | Method of masking corrupt bits during signature analysis and circuit for use therewith | — | 2004-06-01 |