Issued Patents All Time
Showing 1–25 of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12314207 | High bandwidth IJTAG through high speed parallel bus | Jan Burchard, Jonathan Gaudet | 2025-05-27 |
| 11789487 | Asynchronous interface for transporting test-related data via serial channels | Benoit Nadeau-Dostie | 2023-10-17 |
| 11614487 | Multi-capture at-speed scan test based on a slow clock signal | — | 2023-03-28 |
| 11085965 | Clock gating and scan clock generation for circuit test | — | 2021-08-10 |
| 11042181 | Local clock injection and independent capture for circuit test of multiple cores in clock mesh architecture | — | 2021-06-22 |
| 10788530 | Efficient and flexible network for streaming data in circuits | Mark Kassab, Janusz Rajski | 2020-09-29 |
| 10775436 | Streaming networks efficiency using data throttling | Mark Kassab, Janusz Rajski | 2020-09-15 |
| 10473721 | Data streaming for testing identical circuit blocks | Mark Kassab, Janusz Rajski | 2019-11-12 |
| 10476740 | Data generation for streaming networks in circuits | Mark Kassab, Janusz Rajski | 2019-11-12 |
| 9389944 | Test access architecture for multi-die circuits | Ronald Press, Etienne Racine, Martin Keim | 2016-07-12 |
| 9389945 | Test access architecture for stacked dies | Ronald Press, Etienne Racine, Martin Keim | 2016-07-12 |
| 8619077 | Efficient execution of color space processing functions in a graphics processing unit | Jean-Jacques Ostiguy | 2013-12-31 |
| 8516317 | Methods for at-speed testing of memory interface | Benoit Nadeau-Dostie | 2013-08-20 |
| 7757135 | Method and apparatus for storing and distributing memory repair information | Benoit Nadeau-Dostie | 2010-07-13 |
| 7617425 | Method for at-speed testing of memory interface using scan | Benoit Nadeau-Dostie | 2009-11-10 |
| 7424656 | Clocking methodology for at-speed testing of scan circuits with synchronous clocks | Benoit Nadeau-Dostie, Fadi Maamari | 2008-09-09 |
| 7370251 | Method and circuit for collecting memory failure information | Benoit Nadeau-Dostie | 2008-05-06 |
| 7155651 | Clock controller for at-speed testing of scan circuits | Benoit Nadeau-Dostie | 2006-12-26 |
| 7129962 | Efficient video processing method and system | Jean-Jacques Ostiguy | 2006-10-31 |
| 7103860 | Verification of embedded test structures in circuit designs | Paul Price, Ajit Kumar Verma | 2006-09-05 |
| 6952211 | Motion compensation using shared resources of a graphics processor unit | Jean-Jacques Ostiguy | 2005-10-04 |
| 6868532 | Method and program product for designing hierarchical circuit for quiescent current testing and circuit produced thereby | Benoit Nadeau-Dostie | 2005-03-15 |
| 6829730 | Method of designing circuit having multiple test access ports, circuit produced thereby and method of using same | Benoit Nadeau-Dostie | 2004-12-07 |
| 6763489 | Method for scan testing of digital circuit, digital circuit for use therewith and program product for incorporating test methodology into circuit description | Benoit Nadeau-Dostie | 2004-07-13 |
| 6760874 | Test access circuit and method of accessing embedded test controllers in integrated circuit modules | Benoit Nadeau-Dostie | 2004-07-06 |