Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9689918 | Test access architecture for stacked memory and logic dies | Wu-Tung Cheng, Ruifeng Guo, Yu Huang, Liyang Lai, Etienne Racine +3 more | 2017-06-27 |
| 9389944 | Test access architecture for multi-die circuits | Etienne Racine, Martin Keim, Jean-Francois Cote | 2016-07-12 |
| 9389945 | Test access architecture for stacked dies | Etienne Racine, Martin Keim, Jean-Francois Cote | 2016-07-12 |
| 7487419 | Reduced-pin-count-testing architectures for applying test patterns | Nilanjan Mukherjee, Jay Babak Jahangiri, Wu-Tung Cheng | 2009-02-03 |
| 6452426 | Circuit for switching between multiple clocks | Nagesh Tamarapalli | 2002-09-17 |