| 9689918 |
Test access architecture for stacked memory and logic dies |
Wu-Tung Cheng, Ruifeng Guo, Yu Huang, Etienne Racine, Martin Keim +3 more |
2017-06-27 |
| 9335376 |
Test architecture for characterizing interconnects in stacked designs |
Wu-Tung Cheng, Ruifeng Guo, Yu Huang, Jing Ye, Yu Hu |
2016-05-10 |
| 9222978 |
Two-dimensional scan architecture |
Yu Huang, Wu-Tung Cheng, Ruifeng Guo, Manish Sharma |
2015-12-29 |
| 9086459 |
Detection and diagnosis of scan cell internal defects |
Ruifeng Guo, Yu Huang, Wu-Tung Cheng |
2015-07-21 |
| 9015543 |
Diagnosis-aware scan chain stitching |
Yu Huang, Wu-Tung Cheng, Ruifeng Guo |
2015-04-21 |
| 8862956 |
Compound hold-time fault diagnosis |
Yu Huang, Wu-Tung Cheng, Ting-Pu Tai, Ruifeng Guo |
2014-10-14 |
| 7840865 |
Built-in self-test of integrated circuits using selectable weighting of test patterns |
Wu-Tung Cheng, Thomas Hans Rinderknecht |
2010-11-23 |