Issued Patents All Time
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date | Approx Value ⓘ |
|---|---|---|---|---|
| 9689918 | Test access architecture for stacked memory and logic dies | Wu-Tung Cheng, Ruifeng Guo, Yu Huang, Liyang Lai, Etienne Racine +3 more | 2017-06-27 | |
| 9335376 | Test architecture for characterizing interconnects in stacked designs | Wu-Tung Cheng, Ruifeng Guo, Yu Huang, Liyang Lai, Jing Ye | 2016-05-10 | $5,221,000 |
| 7788624 | Methods of balancing logic resource usage in a programmable logic device | Satyaki Das | 2010-08-31 | $4,743,000 |
| 7636907 | Balancing logic resource usage in a programmable integrated circuit | Satyaki Das | 2009-12-22 | $4,374,000 |