Issued Patents All Time
Showing 25 most recent of 92 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12423489 | Modifying a finite element mesh | Jean Cabello, Jonathan Makem, Wafa Daldoul | 2025-09-23 |
| 11815555 | Universal compactor architecture for testing circuits | Yingdi Liu, Janusz Rajski, Grzegorz Mrugalski, Jerzy Tyszer, Bartosz Wlodarczak | 2023-11-14 |
| 11763526 | Multizone quadrilateral mesh generator for high mesh quality and isotropy | — | 2023-09-19 |
| 11585853 | Trajectory-optimized test pattern generation for built-in self-test | Grzegorz Mrugalski, Janusz Rajski, Lukasz Rybak, Jerzy Tyszer | 2023-02-21 |
| 11555854 | Deterministic stellar built-in self test | Yingdi Liu, Janusz Rajski, Jerzy Tyszer | 2023-01-17 |
| 11494982 | Feature based abstraction and meshing | Jonathan Makem, Debashis Basu, Abinesh Thota, Harold T. Fogg | 2022-11-08 |
| 11232246 | Layout-friendly test pattern decompressor | Yu Huang, Janusz Rajski, Mark Kassab, Jeffrey Carl Mayer | 2022-01-25 |
| 11126766 | System and method for element quality improvement in 3D quadrilateral-dominant surface meshes | Jonathan Makem | 2021-09-21 |
| 10963612 | Scan cell architecture for improving test coverage and reducing test application time | Jedrzej Solecki, Janusz Rajski | 2021-03-30 |
| 10955460 | Test scheduling and test access in test compression environment | Mark Kassab, Grzegorz Mrugalski, Janusz Rajski, Jakub Janicki, Jerzy Tyszer | 2021-03-23 |
| 10956625 | Mesh generation system and method | Jonathan Makem | 2021-03-23 |
| 10509072 | Test application time reduction using capture-per-cycle test points | Janusz Rajski, Sylwester Milewski, Jedrzej Solecki, Jerzy Tyszer, Justyna Zawada | 2019-12-17 |
| 10444282 | Test point insertion for low test pattern counts | Janusz Rajski, Elham K. Moghaddam, Jerzy Tyszer, Justyna Zawada | 2019-10-15 |
| 10361873 | Test point-enhanced hardware security | Janusz Rajski, Elham K. Moghaddam, Jerzy Tyszer, Justyna Zawada | 2019-07-23 |
| 10277422 | Virtual port support in a logical switch architecture | Ashok N. Chippa, Ioana M. Costea, Vipin Garg, Sze-Wa Lao, Dar-Ren Leu +4 more | 2019-04-30 |
| 10234506 | Continuous application and decompression of test patterns and selective compaction of test responses | Janusz Rajski, Jerzy Tyszer, Mark Kassab | 2019-03-19 |
| 10148569 | Layer 2 packet switching without look-up table for Ethernet switches | Sushma Anantharam, Keshav G. Kamble, Dar-Ren Leu, Vijoy A. Pandey | 2018-12-04 |
| 9874606 | Selective per-cycle masking of scan chains for system level test | Janusz Rajski, Dariusz Czysz, Grzegorz Mrugalski | 2018-01-23 |
| 9787608 | Unified fabric port | Jayakrishna Kidambi, Vijoy A. Pandey | 2017-10-10 |
| 9781036 | Emulating end-host mode forwarding behavior | Claude Basso | 2017-10-03 |
| 9736163 | Scalable virtual appliance cloud (SVAC) and methods usable in an SVAC | Keshav G. Kamble, Dar-Ren Leu, Vijoy A. Pandey | 2017-08-15 |
| 9722922 | Switch routing table utilizing software defined network (SDN) controller programmed route segregation and prioritization | Dayavanti G. Kamath, Abhijit P. Kumbhare, Vijoy A. Pandey | 2017-08-01 |
| 9664739 | Continuous application and decompression of test patterns and selective compaction of test responses | Janusz Rasjki, Jerzy Tyszer, Mark Kassab | 2017-05-30 |
| 9651622 | Isometric test compression with low toggling activity | Janusz Rajski, Amit Amar Kumar, Mark Kassab, Elham K. Moghaddam, Jerzy Tyszer +1 more | 2017-05-16 |
| 9497073 | Distributed link aggregation group (LAG) for a layer 2 fabric | Dayavanti G. Kamath, Keshav G. Kamble, Dar-Ren Leu, Vijoy A. Pandey | 2016-11-15 |