JT

Jerzy Tyszer

MG Mentor Graphics: 48 patents #3 of 698Top 1%
SS Siemens Industry Software: 4 patents #20 of 391Top 6%
Nortel Networks Limited: 1 patents #2,518 of 5,294Top 50%
Overall (All Time): #21,115 of 4,157,543Top 1%
83
Patents All Time

Issued Patents All Time

Showing 25 most recent of 83 patents

Patent #TitleCo-InventorsDate
11815555 Universal compactor architecture for testing circuits Yingdi Liu, Nilanjan Mukherjee, Janusz Rajski, Grzegorz Mrugalski, Bartosz Wlodarczak 2023-11-14
11585853 Trajectory-optimized test pattern generation for built-in self-test Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Lukasz Rybak 2023-02-21
11555854 Deterministic stellar built-in self test Yingdi Liu, Nilanjan Mukherjee, Janusz Rajski 2023-01-17
11150299 Flexible isometric decompressor architecture for test compression Janusz Rajski, Yu Huang, Sylwester Milewski 2021-10-19
10955460 Test scheduling and test access in test compression environment Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jakub Janicki 2021-03-23
10509072 Test application time reduction using capture-per-cycle test points Janusz Rajski, Sylwester Milewski, Nilanjan Mukherjee, Jedrzej Solecki, Justyna Zawada 2019-12-17
10444282 Test point insertion for low test pattern counts Janusz Rajski, Elham K. Moghaddam, Nilanjan Mukherjee, Justyna Zawada 2019-10-15
10379161 Scan chain stitching for test-per-clock Janusz Rajski, Jedrzej Solecki, Grzegorz Mrugalski 2019-08-13
10361873 Test point-enhanced hardware security Janusz Rajski, Nilanjan Mukherjee, Elham K. Moghaddam, Justyna Zawada 2019-07-23
10234506 Continuous application and decompression of test patterns and selective compaction of test responses Janusz Rajski, Mark Kassab, Nilanjan Mukherjee 2019-03-19
10120024 Multi-stage test response compactors Janusz Rajski, Grzegorz Mrugalski, Mark Kassab, Wu-Tung Cheng 2018-11-06
10120029 Low power testing based on dynamic grouping of scan Janusz Rajski, Sylwester Milewski, Grzegorz Mrugalski 2018-11-06
9933485 Deterministic built-in self-test based on compressed test patterns stored on chip and their derivatives Grzegorz Mrugalski, Janusz Rajski, Lukasz Rybak, Jedrzej Solecki 2018-04-03
9778316 Multi-stage test response compactors Janusz Rajski, Grzegorz Mrugalski, Mark Kassab, Wu-Tung Cheng 2017-10-03
9720041 Scan-based test architecture for interconnects in stacked designs Janusz Rajski 2017-08-01
9714981 Test-per-clock based on dynamically-partitioned reconfigurable scan chains Janusz Rajski, Jedrzej Solecki, Grzegorz Mrugalski 2017-07-25
9664739 Continuous application and decompression of test patterns and selective compaction of test responses Janusz Rasjki, Mark Kassab, Nilanjan Mukherjee 2017-05-30
9651622 Isometric test compression with low toggling activity Janusz Rajski, Amit Amar Kumar, Mark Kassab, Elham K. Moghaddam, Nilanjan Mukherjee +1 more 2017-05-16
9377508 Selective per-cycle masking of scan chains for system level test Janusz Rajski, Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee 2016-06-28
9347993 Test generation for test-per-clock Janusz Rajski, Jedrzej Solecki, Grzegorz Mrugalski 2016-05-24
9335377 Test-per-clock based on dynamically-partitioned reconfigurable scan chains Janusz Rajski, Jedrzej Solecki, Grzegorz Mrugalski 2016-05-10
9250287 On-chip comparison and response collection tools and techniques Nilanjan Mukherjee, Janusz Rajski 2016-02-02
9134370 Continuous application and decompression of test patterns and selective compaction of test responses Janusz Rajski, Mark Kassab, Nilanjan Mukherjee 2015-09-15
9088522 Test scheduling with pattern-independent test access mechanism Janusz Rajski, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Jakub Janicki +1 more 2015-07-21
9009553 Scan chain configuration for test-per-clock based on circuit topology Janusz Rajski, Jedrzej Solecki, Grzegorz Mrugalski 2015-04-14