Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10963612 | Scan cell architecture for improving test coverage and reducing test application time | Nilanjan Mukherjee, Janusz Rajski | 2021-03-30 |
| 10509072 | Test application time reduction using capture-per-cycle test points | Janusz Rajski, Sylwester Milewski, Nilanjan Mukherjee, Jerzy Tyszer, Justyna Zawada | 2019-12-17 |
| 10379161 | Scan chain stitching for test-per-clock | Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski | 2019-08-13 |
| 9933485 | Deterministic built-in self-test based on compressed test patterns stored on chip and their derivatives | Grzegorz Mrugalski, Janusz Rajski, Lukasz Rybak, Jerzy Tyszer | 2018-04-03 |
| 9714981 | Test-per-clock based on dynamically-partitioned reconfigurable scan chains | Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski | 2017-07-25 |
| 9347993 | Test generation for test-per-clock | Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski | 2016-05-24 |
| 9335377 | Test-per-clock based on dynamically-partitioned reconfigurable scan chains | Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski | 2016-05-10 |
| 9009553 | Scan chain configuration for test-per-clock based on circuit topology | Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski | 2015-04-14 |
| 9003248 | Fault-driven scan chain configuration for test-per-clock | Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski | 2015-04-07 |