JT

Jerzy Tyszer

MG Mentor Graphics: 48 patents #3 of 698Top 1%
SS Siemens Industry Software: 4 patents #20 of 391Top 6%
Nortel Networks Limited: 1 patents #2,518 of 5,294Top 50%
Overall (All Time): #21,115 of 4,157,543Top 1%
83
Patents All Time

Issued Patents All Time

Showing 26–50 of 83 patents

Patent #TitleCo-InventorsDate
9003248 Fault-driven scan chain configuration for test-per-clock Janusz Rajski, Jedrzej Solecki, Grzegorz Mrugalski 2015-04-07
8914694 On-chip comparison and response collection tools and techniques Nilanjan Mukherjee, Janusz Rajski 2014-12-16
8832512 Low power compression of incompatible test cubes Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Przemyslaw Szczerbicki 2014-09-09
8726113 Selective per-cycle masking of scan chains for system level test Janusz Rajski, Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee 2014-05-13
8683280 Test generator for low power built-in self-test Janusz Rajski, Grzegorz Mrugalski, Benoit Nadeau-Dostie 2014-03-25
8533547 Continuous application and decompression of test patterns and selective compaction of test responses Janusz Rajski, Mark Kassab, Nilanjan Mukherjee 2013-09-10
8418007 On-chip comparison and response collection tools and techniques Nilanjan Mukherjee, Janusz Rajski 2013-04-09
8356222 Fault diagnosis for non-volatile memories Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski 2013-01-15
8347159 Compression based on deterministic vector clustering of incompatible test cubes Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Dariusz Czysz 2013-01-01
8301945 Decompressors for low power decompression of test patterns Janusz Rajski, Grzegorz Mrugalski, Dariusz Czysz 2012-10-30
8290738 Low power scan testing techniques and apparatus Xijiang Lin, Dariusz Czysz, Mark Kassab, Grzegorz Mrugalski, Janusz Rajski 2012-10-16
8166359 Selective per-cycle masking of scan chains for system level test Janusz Rajski, Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee 2012-04-24
8108743 Method and apparatus for selectively compacting test responses Janusz Rajski, Mark Kassab, Nilanjan Mukherjee 2012-01-31
8046653 Low power decompression of test cubes Janusz Rajski, Grzegorz Mrugalski, Dariusz Czysz 2011-10-25
8024387 Method for synthesizing linear finite state machines Janusz Rajski, Mark Kassab, Nilanjan Mukherjee 2011-09-20
8015461 Decompressors for low power decompression of test patterns Janusz Rajski, Grzegorz Mrugalski, Dariusz Czysz 2011-09-06
7962820 Fault diagnosis of compressed test responses Janusz Rajski, Grzegorz Mrugalski, Artur Pogiel, Chen Wang 2011-06-14
7925465 Low power scan testing techniques and apparatus Xijiang Lin, Dariusz Czysz, Mark Kassab, Grzegorz Mrugalski, Janusz Rajski 2011-04-12
7913137 On-chip comparison and response collection tools and techniques Nilanjan Mukherjee, Janusz Rajski 2011-03-22
7900104 Test pattern compression for an integrated circuit test environment Janusz Rajski, Mark Kassab, Nilanjan Mukherjee 2011-03-01
7890827 Compressing test responses using a compactor Janusz Rajski, Chen Wang, Grzegorz Mrugalski, Artur Pogiel 2011-02-15
7877656 Continuous application and decompression of test patterns to a circuit-under-test Janusz Rajski, Mark Kassab, Nilanjan Mukherjee 2011-01-25
7865794 Decompressor/PRPG for applying pseudo-random and deterministic test patterns Janusz Rajski, Mark Kassab, Nilanjan Mukherjee 2011-01-04
7818644 Multi-stage test response compactors Janusz Rajski, Grzegorz Mrugalski, Mark Kassab, Wu-Tung Cheng 2010-10-19
7805649 Method and apparatus for selectively compacting test responses Janusz Rajski, Mark Kassab, Nilanjan Mukherjee 2010-09-28