XL

Xijiang Lin

MG Mentor Graphics: 17 patents #12 of 698Top 2%
SS Siemens Industry Software: 1 patents #111 of 391Top 30%
NE Nec: 1 patents #50 of 91Top 55%
Overall (All Time): #219,451 of 4,157,543Top 6%
20
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
11635462 Library cell modeling for transistor-level test pattern generation Wu-Tung Cheng, Takeo Kobayashi, Andreas Glowatz 2023-04-25
10977400 Deterministic test pattern generation for designs with timing exceptions Wu-Tung Cheng, Kun-Han Tsai, Naixing Wang, Chen Wang, Mark Kassab +1 more 2021-04-13
10509073 Timing-aware test generation and fault simulation Kun-Han Tsai, Mark Kassab, Chen Wang, Janusz Rajski 2019-12-17
10372855 Scan cell selection for partial scan designs Ting-Pu Tai, Wu-Tung Cheng, Takeo Kobayashi 2019-08-06
10222420 Transition test generation for detecting cell internal defects Wu-Tung Cheng, Janusz Rajski 2019-03-05
9720040 Timing-aware test generation and fault simulation Kun-Han Tsai, Mark Kassab, Chen Wang, Janusz Rajski 2017-08-01
9568552 Logic built-in self-test with high test coverage and low switching activity Janusz Rajski 2017-02-14
9501589 Identification of power sensitive scan cells Yu Huang, Wu-Tung Cheng 2016-11-22
9335374 Dynamic shift for test pattern compression Mark Kassab, Janusz Rajski 2016-05-10
9086454 Timing-aware test generation and fault simulation Kun-Han Tsai, Mark Kassab, Chen Wang, Janusz Rajski 2015-07-21
8996941 Test data volume reduction based on test cube properties Janusz Rajski 2015-03-31
8890563 Scan cell use with reduced power consumption Janusz Rajski 2014-11-18
8560906 Timing-aware test generation and fault simulation Kun-Han Tsai, Mark Kassab, Chen Wang, Janusz Rajski 2013-10-15
8499209 At-speed scan testing with controlled switching activity Janusz Rajski, Elham K. Moghaddam, Nilanjan Mukherjee, Mark Kassab 2013-07-30
8290738 Low power scan testing techniques and apparatus Dariusz Czysz, Mark Kassab, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer 2012-10-16
8051352 Timing-aware test generation and fault simulation Kun-Han Tsai, Mark Kassab, Chen Wang, Janusz Rajski 2011-11-01
7925465 Low power scan testing techniques and apparatus Dariusz Czysz, Mark Kassab, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer 2011-04-12
7865792 Test generation methods for reducing power dissipation and supply currents Janusz Rajski 2011-01-04
7685491 Test generation methods for reducing power dissipation and supply currents Janusz Rajski 2010-03-23
6378096 On-line partitioning for sequential circuit test generation Srimat Chakradhar, Kiran B. Doreswamy, Surendra K. Bommu 2002-04-23