KT

Kun-Han Tsai

MG Mentor Graphics: 11 patents #21 of 698Top 4%
SS Siemens Industry Software: 2 patents #51 of 391Top 15%
Overall (All Time): #291,422 of 4,157,543Top 8%
16
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
11681843 Input data compression for machine learning-based chain diagnosis Yu Huang, Gaurav Veda, Wu-Tung Cheng, Mason Chern, Shi-Yu Huang 2023-06-20
11361248 Multi-stage machine learning-based chain diagnosis Yu Huang, Gaurav Veda, Wu-Tung Cheng, Mason Chern, Shi-Yu Huang 2022-06-14
10977400 Deterministic test pattern generation for designs with timing exceptions Wu-Tung Cheng, Naixing Wang, Chen Wang, Xijiang Lin, Mark Kassab +1 more 2021-04-13
10509073 Timing-aware test generation and fault simulation Xijiang Lin, Mark Kassab, Chen Wang, Janusz Rajski 2019-12-17
10317462 Wide-range clock signal generation for speed grading of logic cores Shi-Yu Huang, Wu-Tung Cheng, Tzu-Heng Huang 2019-06-11
9720040 Timing-aware test generation and fault simulation Xijiang Lin, Mark Kassab, Chen Wang, Janusz Rajski 2017-08-01
9720038 Method and circuit of pulse-vanishing test Shi-Yu Huang, Wu-Tung Cheng, Jeo-Yen Lee 2017-08-01
9086454 Timing-aware test generation and fault simulation Xijiang Lin, Mark Kassab, Chen Wang, Janusz Rajski 2015-07-21
8560906 Timing-aware test generation and fault simulation Xijiang Lin, Mark Kassab, Chen Wang, Janusz Rajski 2013-10-15
8527232 Diagnostic test pattern generation for small delay defect Ruifeng Guo, Wu-Tung Cheng, Takeo Kobayashi 2013-09-03
8468409 Speed-path debug using at-speed scan test patterns Ruifeng Guo, Wu-Tung Cheng 2013-06-18
8301414 Compactor independent fault diagnosis Wu-Tung Cheng, Yu Huang, Nagesh Tamarapalli, Janusz Rajski 2012-10-30
8051352 Timing-aware test generation and fault simulation Xijiang Lin, Mark Kassab, Chen Wang, Janusz Rajski 2011-11-01
7984354 Generating responses to patterns stimulating an electronic circuit with timing exception paths Dhiraj Goswami, Mark Kassab, Janusz Rajski 2011-07-19
7555689 Generating responses to patterns stimulating an electronic circuit with timing exception paths Dhiraj Goswami, Mark Kassab, Janusz Rajski 2009-06-30
7239978 Compactor independent fault diagnosis Wu-Tung Cheng, Yu Huang, Nagesh Tamarapalli, Janusz Rajski 2007-07-03