Issued Patents All Time
Showing 26–41 of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6738938 | Method for collecting failure information for a memory using an embedded test controller | Benoit Nadeau-Dostie | 2004-05-18 |
| 6725435 | Method and program product for completing a circuit design having embedded test structures | Paul Price | 2004-04-20 |
| 6678875 | Self-contained embedded test design environment and environment setup utility | Brian John Pajak, Paul Price, Luc Romain | 2004-01-13 |
| 6671839 | Scan test method for providing real time identification of failing test patterns and test bist controller for use therewith | Benoit Nadeau-Dostie | 2003-12-30 |
| 6615392 | Hierarchical design and test method and system, program product embodying the method and integrated circuit produced thereby | Benoit Nadeau-Dostie, Dwayne Burek, Sonny Ngai San Shum, Pierre Girouard, Pierre Gauther +3 more | 2003-09-02 |
| 6614263 | Method and circuitry for controlling clocks of embedded blocks during logic bist test mode | Benoit Nadeau-Dostie | 2003-09-02 |
| 6536008 | Fault insertion method, boundary scan cells, and integrated circuit for use therewith | Benoit Nadeau-Dostie, Pierre Gauthier | 2003-03-18 |
| 6510534 | Method and apparatus for testing high performance circuits | Benoit Nadeau-Dostie, Fadi Maamari, Dwayne Burek | 2003-01-21 |
| 6330681 | Method and apparatus for controlling power level during BIST | Benoit Nadeau-Dostie, Pierre Gauthier | 2001-12-11 |
| 6327684 | Method of testing at-speed circuits having asynchronous clocks and controller for use therewith | Benoit Nadeau-Dostie, Naader Hasani | 2001-12-04 |
| 6145105 | Method and apparatus for scan testing digital circuits | Benoit Nadeau-Dostie, Dwayne Burek | 2000-11-07 |
| 6115827 | Clock skew management method and apparatus | Benoit Nadeau-Dostie | 2000-09-05 |
| 6046946 | Method and apparatus for testing multi-port memory using shadow read | Benoit Nadeau-Dostie | 2000-04-04 |
| 6000051 | Method and apparatus for high-speed interconnect testing | Benoit Nadeau-Dostie | 1999-12-07 |
| 5900753 | Asynchronous interface | Benoit Nadeau-Dostie | 1999-05-04 |
| 5812469 | Method and apparatus for testing multi-port memory | Benoit Nadeau-Dostie | 1998-09-22 |