Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10599800 | Formal clock network analysis, visualization, verification and generation | Mohamed Shaker Sarwary, Hans-Joerg Peter, Guillaume Plassan, Barsneya Chakrabarti | 2020-03-24 |
| 9721057 | System and method for netlist clock domain crossing verification | Malay Ganai, Mohamed Shaker Sarwary, Maher Mneimneh, Paras Mal Jain, Pronay Kumar Biswas +1 more | 2017-08-01 |
| 9721058 | System and method for reactive initialization based formal verification of electronic logic design | Mohamed Shaker Sarwary, Hans-Jorg Peter, Barsneya Chakrabarti, Fahim Rahim | 2017-08-01 |
| 9201992 | Method and apparatus using formal methods for checking generated-clock timing definitions | Sridhar Gangadharan, Barsneya Chakrabarti, Manish Goel | 2015-12-01 |
| 8984457 | System and method for a hybrid clock domain crossing verification | Mohamed Shaker Sarwary, Maher Mneimneh | 2015-03-17 |
| 8984469 | System and method for strengthening of a circuit element to reduce an integrated circuit's power consumption | Solaiman Rahim, Siddharth Guha, Vaibhav Jain | 2015-03-17 |
| 8856706 | System and method for metastability verification of circuits of an integrated circuit | Maher Mneimneh, Shaker Sarwary, Paras Mal Jain, Ashish Bansal, Namit Gupta | 2014-10-07 |
| 8788993 | Computer system for generating an integrated and unified view of IP-cores for hierarchical analysis of a system on chip (SoC) design | Sridhar Gangadharan, Shaker Sarwary, Fadi Maamari, Subir Chandra Ray | 2014-07-22 |
| 8739087 | System and method for large multiplexer identification and creation in a design of an integrated circuit | Tien-Chien Lee, Saurabh Verma, Satrajit Pal, Chandra Prakash Manglani, Jitendra Kumar | 2014-05-27 |
| 8677295 | Sequential clock gating using net activity and xor technique on semiconductor designs including already gated pipeline design | Solaiman Rahim | 2014-03-18 |
| 8656326 | Sequential clock gating using net activity and XOR technique on semiconductor designs including already gated pipeline design | Solaiman Rahim | 2014-02-18 |
| 8635578 | System and method for strengthening of a circuit element to reduce an integrated circuit's power consumption | Solaiman Rahim, Siddharth Guha, Vaibhav Jain | 2014-01-21 |
| 8607173 | Hierarchical bottom-up clock domain crossing verification | Mohamed Shaker Sarwary, Maher Mneimneh, Paras Mal Jain, Deepak P. Ahuja | 2013-12-10 |
| 8533647 | Method for generating an integrated and unified view of IP-cores for hierarchical analysis of a system on chip (SoC) design | Sridhar Gangadharan, Shaker Sarwary, Fadi Maamari, Subir Ray | 2013-09-10 |
| 8448111 | System and method for metastability verification of circuits of an integrated circuit | Maher Mneimneh, Shaker Sarwary, Paras Mal Jain, Ashish Bansal, Namit Gupta | 2013-05-21 |