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Default to signed-in state |
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Reset domain crossing management using unified power format |
Deep Shah, Mohamed Shaker Sarwary |
2019-05-14 |
| 9990453 |
Clock-domain-crossing specific design mutations to model silicon behavior and measure verification robustness |
Jean-Marc A. Forey, Mahantesh D. Narwade, Horia Alexandru Toma |
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| 9886753 |
Verification of circuit structures including sub-structure variants |
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| 9792394 |
Accurate glitch detection |
Kaushik De, Dipti Ranjan Senapati, Mahantesh D. Narwade, Rajarshi Mukherjee |
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| 9529948 |
Minimizing crossover paths for functional verification of a circuit description |
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2016-12-27 |
| 8856706 |
System and method for metastability verification of circuits of an integrated circuit |
Maher Mneimneh, Shaker Sarwary, Paras Mal Jain, Ashish Bansal, Mohammad H. Movahed-Ezazi |
2014-10-07 |
| 8448111 |
System and method for metastability verification of circuits of an integrated circuit |
Maher Mneimneh, Shaker Sarwary, Paras Mal Jain, Ashish Bansal, Mohammad H. Movahed-Ezazi |
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