Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Namit Gupta — 9 Patents

SYSynopsys: 5 patents #244 of 2,302Top 15%
ATAtrenta: 2 patents #19 of 68Top 30%
Microsoft: 2 patents #17,644 of 40,388Top 45%
San Jose, CA: #7,016 of 32,062 inventorsTop 25%
California: #67,547 of 386,348 inventorsTop 20%
Overall (All Time): #535,341 of 4,157,543Top 15%
9 Patents All Time
Namit Gupta has been granted 9 US patents while listed as an inventor at Synopsys. The first was granted in 2013 and the most recent in December 2021. Namit Gupta ranks #535,341 of 4,157,543 US inventors in our database (top 12.9%). Patent records list Namit Gupta in San Jose, CA, US.

Issued Patents All Time

Showing 1–9 of 9 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
11212282 Connected [i.e. linked] accounts of a user keeps signed state in alive of other connected [i.e. linked] accounts Akshay Navneetlal Mutha, Rohit Dilip Mahale, Alexandra Veronica Rinja 2021-12-28 $185,798,000
10715523 Default to signed-in state Akshay Navneetlal Mutha 2020-07-14 $94,985,000
10289773 Reset domain crossing management using unified power format Deep Shah, Mohamed Shaker Sarwary 2019-05-14 $18,780,000
9990453 Clock-domain-crossing specific design mutations to model silicon behavior and measure verification robustness Jean-Marc A. Forey, Mahantesh D. Narwade, Horia Alexandru Toma 2018-06-05 $21,668,000
9886753 Verification of circuit structures including sub-structure variants Mahantesh D. Narwade, Kaushik De, Rajarshi Mukherjee, Suman Nandan, Subhamoy Pal 2018-02-06 $39,140,000
9792394 Accurate glitch detection Kaushik De, Dipti Ranjan Senapati, Mahantesh D. Narwade, Rajarshi Mukherjee 2017-10-17 $13,665,000
9529948 Minimizing crossover paths for functional verification of a circuit description Kaushik De, Mahantesh D. Narwade, Rajarshi Mukherjee 2016-12-27 $26,399,000
8856706 System and method for metastability verification of circuits of an integrated circuit Maher Mneimneh, Shaker Sarwary, Paras Mal Jain, Ashish Bansal, Mohammad H. Movahed-Ezazi 2014-10-07
8448111 System and method for metastability verification of circuits of an integrated circuit Maher Mneimneh, Shaker Sarwary, Paras Mal Jain, Ashish Bansal, Mohammad H. Movahed-Ezazi 2013-05-21