| 12393754 |
Generating a reduced block model view on-the-fly |
Mahantesh D. Narwade, Soumen Ghosh, Mark Roizman, Vijaya V. Varkey, Abhinav Singla |
2025-08-19 |
| 11907631 |
Reset domain crossing detection and simulation |
Fahim Rahim, Paras Mal Jain, Deep Shah, Satrajit Pal, Dipit Ranjan Senapati +1 more |
2024-02-20 |
| 11886877 |
Memory select register to simplify operand mapping in subroutines |
Richard T. Witek, Peter Charles Eastty |
2024-01-30 |
| 11556406 |
Automatic root cause analysis of complex static violations by static information repository exploration |
Aditya Vikram Daga, Sauresh Bhowmick, Bhaskar Pal |
2023-01-17 |
| 11467851 |
Machine learning (ML)-based static verification for derived hardware-design elements |
Kaushik De, Paras Mal Jain, David L. Allen |
2022-10-11 |
| 11403450 |
Convergence centric coverage for clock domain crossing (CDC) jitter in simulation |
Anshu Malani, Paras Mal Jain, Sudeep Mondal |
2022-08-02 |
| 11288427 |
Automated root-cause analysis, visualization, and debugging of static verification results |
Sauresh Bhowmick, Sanjay Gulati, Sourasis Das, Bhaskar Pal |
2022-03-29 |
| 11222154 |
State table complexity reduction in a hierarchical verification flow |
Kaushik De, David L. Allen, Bhaskar Pal, Sanjay Gulati, Gaurav PRATAP +3 more |
2022-01-11 |
| 10831961 |
Automated coverage convergence by correlating random variables with coverage variables sampled from simulation result data |
Esha Dutta, Danish Jawed, Bhaskar Pal, Parijat Biswas, Pravash Chandra Dash +1 more |
2020-11-10 |
| 10586001 |
Automated root-cause analysis, visualization, and debugging of static verification results |
Sauresh Bhowmick, Sanjay Gulati, Sourasis Das, Bhaskar Pal |
2020-03-10 |
| 10460059 |
System and method for generating reduced standard delay format files for gate level simulation |
Akash Khandelwal, Pawan Kulshreshtha, Chih-kuo Yu |
2019-10-29 |
| 9886753 |
Verification of circuit structures including sub-structure variants |
Mahantesh D. Narwade, Namit Gupta, Kaushik De, Suman Nandan, Subhamoy Pal |
2018-02-06 |
| 9792394 |
Accurate glitch detection |
Kaushik De, Dipti Ranjan Senapati, Mahantesh D. Narwade, Namit Gupta |
2017-10-17 |
| 9529948 |
Minimizing crossover paths for functional verification of a circuit description |
Kaushik De, Mahantesh D. Narwade, Namit Gupta |
2016-12-27 |
| 9069699 |
Identifying inconsistent constraints |
Dhiraj Goswami, Soe Myint, Ngai Ngai William Hung |
2015-06-30 |
| 9032339 |
Ranking verification results for root cause analysis |
Kaushik De, Kevin M. Harer, Mahantesh D. Narwade |
2015-05-12 |
| 7383168 |
Method and system for design verification and debugging of a complex computing system |
Toshiya Mima, Yozo Nakayama |
2008-06-03 |
| 7350168 |
System, method and computer program product for equivalence checking between designs with sequential differences |
Anmol Mathur, Nikhil Sharma, Deepak Goyal, Gagan Hasteer |
2008-03-25 |
| 7194710 |
Scheduling events in a boolean satisfiability (SAT) solver |
Mukul R. Prasad |
2007-03-20 |
| 7032192 |
Performing latch mapping of sequential circuits |
Mukul R. Prasad, Jawahar Jain, Kelvin Kwok-Cheung Ng |
2006-04-18 |
| 6532440 |
Multiple error and fault diagnosis based on Xlists |
Vamsi Boppana, Jawahar Jain, Masahiro Fujita |
2003-03-11 |
| 6408424 |
Verification of sequential circuits with same state encoding |
Jawahar Jain, Vamsi Boppana |
2002-06-18 |
| 6301687 |
Method for verification of combinational circuits using a filtering oriented approach |
Jawahar Jain, Koichiro Takayama |
2001-10-09 |
| 6086626 |
Method for verification of combinational circuits using a filtering oriented approach |
Jawahar Jain, Koichiro Takayama |
2000-07-11 |
| 5649165 |
Topology-based computer-aided design system for digital circuits and method thereof |
Jawahar Jain |
1997-07-15 |
