Issued Patents All Time
Showing 1–25 of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11886877 | Memory select register to simplify operand mapping in subroutines | Peter Charles Eastty, Rajarshi Mukherjee | 2024-01-30 |
| 10691490 | System for scheduling threads for execution | Peter Charles Eastty | 2020-06-23 |
| 10564931 | Floating-point arithmetic operation range exception override circuit | Brian Clark, Peter Charles Eastty | 2020-02-18 |
| 10243581 | System and method for implementing finite impulse response filter in an audio processor | Peter Charles Eastty | 2019-03-26 |
| 9658675 | Achieving power saving by a circuit including pluralities of processing cores based on status of the buffers used by the processing cores | Long Li, Maya Suresh | 2017-05-23 |
| 9658676 | Sending messages in a network-on-chip and providing a low power state for processing cores | Long Li, Maya Suresh | 2017-05-23 |
| 7750912 | Integrating display controller into low power processor | R. Stephen Polzin, Maurice B. Steinman | 2010-07-06 |
| 7395443 | Integrated circuit with a hibernate mode and method therefor | Stephen C. Kromer, James J. Montanaro, Kathryn J. Hoover | 2008-07-01 |
| 7093153 | Method and apparatus for lowering bus clock frequency in a complex integrated data processing system | Suzanne Plummer, James J. Montanaro, Stephen C. Kromer, Kathryn J. Hoover | 2006-08-15 |
| 6167509 | Branch performance in high speed processor | Richard L. Sites | 2000-12-26 |
| 6076158 | Branch prediction in high-performance processor | Richard L. Sites | 2000-06-13 |
| 6061774 | Limited virtual address aliasing and fast context switching with multi-set virtual cache without backmaps | — | 2000-05-09 |
| 5995746 | Byte-compare operation for high-performance processor | Richard L. Sites | 1999-11-30 |
| 5943492 | Apparatus and method for generating external interface signals in a microprocessor | David G. Conroy | 1999-08-24 |
| 5778423 | Prefetch instruction for improving performance in reduced instruction set processor | Richard L. Sites | 1998-07-07 |
| 5636366 | System and method for preserving instruction state-atomicity for translated program | Scott Robinson, Richard L. Sites | 1997-06-03 |
| 5568624 | Byte-compare operation for high-performance processor | Richard L. Sites | 1996-10-22 |
| 5469551 | Method and apparatus for eliminating branches using conditional move instructions | Richard L. Sites | 1995-11-21 |
| 5454091 | Virtual to physical address translation scheme with granularity hint for identifying subsequent pages to be accessed | Richard L. Sites | 1995-09-26 |
| 5430888 | Pipeline utilizing an integral cache for transferring data to and from a register | Douglas D. Williams, Timothy J. Stanley, David Fenwick, Douglas J. Burns, Rebecca L. Stamm +1 more | 1995-07-04 |
| 5410682 | In-register data manipulation for unaligned byte write using data shift in reduced instruction set processor | Richard L. Sites | 1995-04-25 |
| 5367705 | In-register data manipulation using data shift in reduced instruction set processor | Richard L. Sites | 1994-11-22 |
| 5341482 | Method for synchronization of arithmetic exceptions in central processing units having pipelined execution units simultaneously executing instructions | David N. Cutler, David A. Orbits, Dileep Bhandarkar, Wayne Cardoza | 1994-08-23 |
| 5319760 | Translation buffer for virtual machines with address space match | Andrew H. Mason, Judith Shelhorse Hall, Paul T. Robinson | 1994-06-07 |
| 5317717 | Apparatus and method for main memory unit protection using access and fault logic signals | David N. Cutler, David A. Orbits, Dileep Bhandarkar, Wayne Cardoza | 1994-05-31 |