Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6675192 | Temporary halting of thread execution until monitoring of armed events to memory location identified in working registers | Joel S. Emer, Bruce E. Edwards, Matthew Reilly, Craig B. Zilles, Tryggve Fossum +2 more | 2004-01-06 |
| 6493741 | Method and apparatus to quiesce a portion of a simultaneous multithreaded central processing unit | Joel S. Emer, Bruce E. Edwards, Matthew Reilly, Craig B. Zilles, Tryggve Fossum +2 more | 2002-12-10 |
| 6470443 | Pipelined multi-thread processor selecting thread instruction in inter-stage buffer based on count information | Joel S. Emer, Trggve Fossum, Robert H. Halstead, Jr., George Z. Chrysos, Dean Tullsen +2 more | 2002-10-22 |
| 6073159 | Thread properties attribute vector based thread selection in multithreading processor | Joel S. Emer, Trggve Fossum, Robert H. Halstead, Jr., George Z. Chrysos, Dean Tullsen +2 more | 2000-06-06 |
| 5481689 | Conversion of internal processor register commands to I/O space addresses | G. Michael Uhler | 1996-01-02 |
| 5432918 | Method and apparatus for ordering read and write operations using conflict bits in a write queue | — | 1995-07-11 |
| 5430888 | Pipeline utilizing an integral cache for transferring data to and from a register | Richard T. Witek, Douglas D. Williams, Timothy J. Stanley, David Fenwick, Douglas J. Burns +1 more | 1995-07-04 |
| 5404483 | Processor and method for delaying the processing of cache coherency transactions during outstanding cache fills | Ruth I. Bahar, Nicholas D. Wade | 1995-04-04 |
| 5404482 | Processor and method for preventing access to a locked memory block by recording a lock in a content addressable memory with outstanding cache fills | Nicholas D. Wade | 1995-04-04 |
| 5347648 | Ensuring write ordering under writeback cache error conditions | Ruth I. Bahar, Raymond L. Strouble, Nicholas D. Wade, John H. Edmondson | 1994-09-13 |
| 5317720 | Processor system with writeback cache using writeback and non writeback transactions stored in separate queues | John H. Edmondson, David W. Archer, Samyojita Nadkarni, Raymond L. Strouble | 1994-05-31 |
| 5155843 | Error transition mode for multi-processor system | R. Iris Bahar, Michael A. Callander, Linda Chao, Derrick R. Meyer, Douglas E. Sanders +3 more | 1992-10-13 |
| 5148536 | Pipeline having an integral cache which processes cache misses and loads data in parallel | Richard T. Witek, Douglas D. Williams, Timothy J. Stanley, David Fenwick, Douglas J. Burns +1 more | 1992-09-15 |
| 5058006 | Method and apparatus for filtering invalidate requests | W. Hugh Durdan, G. Michael Uhler | 1991-10-15 |