Nicholas D. Wade — 21 Patents at Intel

Nicholas D. Wade has been granted 21 US patents while listed as an inventor at Intel. The first was granted in 1992 and the most recent in April 2004. Nicholas D. Wade ranks #201,324 of 4,157,543 US inventors in our database (top 4.8%). Patent records list Nicholas D. Wade in Marlborough, MA, US.

Issued Patents All Time

Showing 1–21 of 21 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
6725349	Method and apparatus for controlling of a memory subsystem installed with standard page mode memory and an extended data out memory	Brian K. Langendorf, James M. Dodd	2004-04-20	$26,995,000
6574219	Passive message ordering on a decentralized ring	Gilbert Neiger, Kai-Yang Cheng	2003-06-03
6505282	Method and apparatus for determining memory types of a multi-type memory subsystem where memory of the different types are accessed using column control signals with different timing characteristics	Brian K. Langendorf, James M. Dodd	2003-01-07	$57,181,000
6393525	Least recently used replacement method with protection	Christopher B. Wilkerson	2002-05-21	$83,641,000
6112283	Out-of-order snooping for multiprocessor computer systems	Gilbert Neiger, Kai Cheng	2000-08-29	$206,201,000
6112016	Method and apparatus for sharing a signal line between agents	Peter D. MacWilliams, Norman J. Rasmussen, William S. Wu	2000-08-29	$206,201,000
5953746	Method and apparatus for dynamically resizing a frame buffer in a shared memory buffer architecture system	Ken M. Crocker, Radhakrishnan Venkataraman	1999-09-14	$149,288,000
5915265	Method and apparatus for dynamically allocating and resizing the dedicated memory in a shared memory buffer architecture system	Ken M. Crocker, Radhakrishnan Venkataraman	1999-06-22	$240,692,000
5828854	Method and apparatus for multiplexing signals from a bus bridge to an ISA bus interface and an ATA bus interface	—	1998-10-27	$71,819,000
5822767	Method and apparartus for sharing a signal line between agents	Peter D. MacWilliams, Norman J. Rasmussen, William S. Wu	1998-10-13	$57,272,000
5818464	Method and apparatus for arbitrating access requests to a shared computer system memory by a graphics controller and memory controller	—	1998-10-06	$51,460,000
5790849	Method and apparatus to permit the boot of a shared memory buffer architecture employing an arbitrary operating system	Ken M. Crocker, Radhakrishnan Venkataraman	1998-08-04	$96,433,000
5717873	Deadlock avoidance mechanism and method for multiple bus topology	Jeffrey L. Rabe, Bruce A. Young	1998-02-10	$94,519,000
5651137	Scalable cache attributes for an input/output bus	Peter D. MacWilliams, Norman J. Rasmussen, William S. Wu	1997-07-22	$275,154,000
5625779	Arbitration signaling mechanism to prevent deadlock guarantee access latency, and guarantee acquisition latency for an expansion bridge	Gary Solomon, Peter D. MacWilliams, George R. Hayek, Abid Asghar	1997-04-29	$143,946,000
5613075	Method and apparatus for providing deterministic read access to main memory in a computer system	Mark Lalich, Bruce A. Young	1997-03-18	$60,088,000
5606672	Method and apparatus for multiplexing signals from a bus bridge to an ISA bus interface and an ATA bus interface	—	1997-02-25	$117,990,000
5404482	Processor and method for preventing access to a locked memory block by recording a lock in a content addressable memory with outstanding cache fills	Rebecca L. Stamm	1995-04-04	$8,753,000
5404483	Processor and method for delaying the processing of cache coherency transactions during outstanding cache fills	Rebecca L. Stamm, Ruth I. Bahar	1995-04-04	$8,753,000
5347648	Ensuring write ordering under writeback cache error conditions	Rebecca L. Stamm, Ruth I. Bahar, Raymond L. Strouble, John H. Edmondson	1994-09-13	$6,790,000
5155843	Error transition mode for multi-processor system	Rebecca L. Stamm, R. Iris Bahar, Michael A. Callander, Linda Chao, Derrick R. Meyer +3 more	1992-10-13	$5,763,000

Nicholas D. Wade — 21 Patents

Issued Patents All Time

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