Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6725349 | Method and apparatus for controlling of a memory subsystem installed with standard page mode memory and an extended data out memory | Brian K. Langendorf, James M. Dodd | 2004-04-20 |
| 6574219 | Passive message ordering on a decentralized ring | Gilbert Neiger, Kai-Yang Cheng | 2003-06-03 |
| 6505282 | Method and apparatus for determining memory types of a multi-type memory subsystem where memory of the different types are accessed using column control signals with different timing characteristics | Brian K. Langendorf, James M. Dodd | 2003-01-07 |
| 6393525 | Least recently used replacement method with protection | Christopher B. Wilkerson | 2002-05-21 |
| 6112283 | Out-of-order snooping for multiprocessor computer systems | Gilbert Neiger, Kai Cheng | 2000-08-29 |
| 6112016 | Method and apparatus for sharing a signal line between agents | Peter D. MacWilliams, Norman J. Rasmussen, William S. Wu | 2000-08-29 |
| 5953746 | Method and apparatus for dynamically resizing a frame buffer in a shared memory buffer architecture system | Ken M. Crocker, Radhakrishnan Venkataraman | 1999-09-14 |
| 5915265 | Method and apparatus for dynamically allocating and resizing the dedicated memory in a shared memory buffer architecture system | Ken M. Crocker, Radhakrishnan Venkataraman | 1999-06-22 |
| 5828854 | Method and apparatus for multiplexing signals from a bus bridge to an ISA bus interface and an ATA bus interface | — | 1998-10-27 |
| 5822767 | Method and apparartus for sharing a signal line between agents | Peter D. MacWilliams, Norman J. Rasmussen, William S. Wu | 1998-10-13 |
| 5818464 | Method and apparatus for arbitrating access requests to a shared computer system memory by a graphics controller and memory controller | — | 1998-10-06 |
| 5790849 | Method and apparatus to permit the boot of a shared memory buffer architecture employing an arbitrary operating system | Ken M. Crocker, Radhakrishnan Venkataraman | 1998-08-04 |
| 5717873 | Deadlock avoidance mechanism and method for multiple bus topology | Jeffrey L. Rabe, Bruce A. Young | 1998-02-10 |
| 5651137 | Scalable cache attributes for an input/output bus | Peter D. MacWilliams, Norman J. Rasmussen, William S. Wu | 1997-07-22 |
| 5625779 | Arbitration signaling mechanism to prevent deadlock guarantee access latency, and guarantee acquisition latency for an expansion bridge | Gary Solomon, Peter D. MacWilliams, George R. Hayek, Abid Asghar | 1997-04-29 |
| 5613075 | Method and apparatus for providing deterministic read access to main memory in a computer system | Mark Lalich, Bruce A. Young | 1997-03-18 |
| 5606672 | Method and apparatus for multiplexing signals from a bus bridge to an ISA bus interface and an ATA bus interface | — | 1997-02-25 |
| 5404482 | Processor and method for preventing access to a locked memory block by recording a lock in a content addressable memory with outstanding cache fills | Rebecca L. Stamm | 1995-04-04 |
| 5404483 | Processor and method for delaying the processing of cache coherency transactions during outstanding cache fills | Rebecca L. Stamm, Ruth I. Bahar | 1995-04-04 |
| 5347648 | Ensuring write ordering under writeback cache error conditions | Rebecca L. Stamm, Ruth I. Bahar, Raymond L. Strouble, John H. Edmondson | 1994-09-13 |
| 5155843 | Error transition mode for multi-processor system | Rebecca L. Stamm, R. Iris Bahar, Michael A. Callander, Linda Chao, Derrick R. Meyer +3 more | 1992-10-13 |