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Apparatus and method for dedicated interconnection over a shared external bus |
Brad W. Hosler, Darren Abramson, Michael J. McTague |
2003-07-15 |
| 6502146 |
Apparatus and method for dedicated interconnection over a shared external bus |
Brad W. Hosler, Darren Abramson, Michael J. McTague |
2002-12-31 |
| 6434692 |
High-throughput interface between a system memory controller and a peripheral device |
William S. Wu |
2002-08-13 |
| 6317803 |
High-throughput interconnect having pipelined and non-pipelined bus transaction modes |
Gary Solomon, David G. Carson, George R. Hayek, Brent S. Baxter, Colyn S. Case |
2001-11-13 |
| 6266719 |
High-throughput interface between a system memory controller and a peripheral device |
William S. Wu |
2001-07-24 |
| 6167468 |
High-throughput interface between a system memory controller and a peripheral device |
William S. Wu |
2000-12-26 |
| 6112016 |
Method and apparatus for sharing a signal line between agents |
Peter D. MacWilliams, Nicholas D. Wade, William S. Wu |
2000-08-29 |
| 6047355 |
Symmetric multiprocessing system with unified environment and distributed system functions |
William S. Wu, Suresh Marisetty, Puthiya K. Nizar |
2000-04-04 |
| 6006291 |
High-throughput interface between a system memory controller and a peripheral device |
William S. Wu |
1999-12-21 |
| 5948094 |
Method and apparatus for executing multiple transactions within a single arbitration cycle |
Gary Solomon, Peter D. MacWilliams |
1999-09-07 |
| 5887194 |
Locking protocol for peripheral component interconnect utilizing master device maintaining assertion of lock signal after relinquishing control of bus such that slave device remains locked |
Dave Carson, Bruce A. Young, Stephen A. Fischer, Jeffrey L. Rabe |
1999-03-23 |
| 5832241 |
Data consistency across a bus transactions that impose ordering constraints |
Charles B. Guy, Bruce A. Young |
1998-11-03 |
| 5822767 |
Method and apparartus for sharing a signal line between agents |
Peter D. MacWilliams, Nicholas D. Wade, William S. Wu |
1998-10-13 |
| 5809340 |
Adaptively generating timing signals for access to various memory devices based on stored profiles |
James F. Bertone, Bruno DiPlacido, Thomas F. Joyce, Martin Massucci, Lance J. McNally +10 more |
1998-09-15 |
| 5768548 |
Bus bridge for responding to received first write command by storing data and for responding to received second write command by transferring the stored data |
Bruce A. Young |
1998-06-16 |
| 5740376 |
Signaling protocol for a peripheral component interconnect |
Dave Carson, Bruce A. Young, Stephen A. Fischer, Jeffrey L. Rabe |
1998-04-14 |
| 5651137 |
Scalable cache attributes for an input/output bus |
Peter D. MacWilliams, Nicholas D. Wade, William S. Wu |
1997-07-22 |
| 5522069 |
Symmetric multiprocessing system with unified environment and distributed system functions |
James F. Bertone, Bruno DiPlacido, Thomas F. Joyce, Martin Massucci, Lance J. McNally +10 more |
1996-05-28 |
| 5467295 |
Bus arbitration with master unit controlling bus and locking a slave unit that can relinquish bus for other masters while maintaining lock on slave unit |
Bruce A. Young, Dave Carson, Stephen A. Fischer, Jeffrey L. Rabe |
1995-11-14 |