Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| D718271 | Digital media player | Daniel Parisien | 2014-11-25 |
| 7190715 | Asymmetric digital subscriber loop modem | Raman Srinivasan, Brad A. Barmore | 2007-03-13 |
| 7028209 | I2C repeater with voltage translation | Daniel A. Mosley | 2006-04-11 |
| 6994229 | Device for dispensing laminar items | Irene C. Power | 2006-02-07 |
| 6931706 | Disk drive preparation jig assembly | Fergal Duffy | 2005-08-23 |
| 6678776 | System for a card proxy link architecture | — | 2004-01-13 |
| 6597197 | I2C repeater with voltage translation | Daniel A. Mosley | 2003-07-22 |
| 6594717 | Apparatus and method for dedicated interconnection over a shared external bus | Norman J. Rasmussen, Brad W. Hosler, Darren Abramson | 2003-07-15 |
| 6549967 | System for a PCI proxy link architecture | — | 2003-04-15 |
| 6502146 | Apparatus and method for dedicated interconnection over a shared external bus | Norman J. Rasmussen, Brad W. Hosler, Darren Abramson | 2002-12-31 |
| 6292865 | Method and apparatus for reducing bus bridge thrashing by temporarily masking agent requests to allow conflicting requests to be completed | Bradford B. Congdon | 2001-09-18 |
| 6282594 | Pallet, system and method for use in testing and/or installing software onto a personal computer system unit | Edward T. O'Shea | 2001-08-28 |
| 6026460 | Method and apparatus for sequencing system bus grants and disabling a posting buffer in a bus bridge to improve bus efficiency | Howard S. David | 2000-02-15 |
| 5850557 | Method and apparatus for reducing bus bridge thrashing by temporarily masking agent requests to allow conflicting requests to be completed | Bradford B. Congdon | 1998-12-15 |
| 5668949 | System utilizing multiple address decode resources and decoder receiving address determines address corresponding to resource based on select and ready signals by that particular resource | Joseph M. Nardone, Howard S. David | 1997-09-16 |
| 5590289 | Method and apparatus for initializing a computer system having central and distributed address decode memory bus resources | Joseph M. Nardone, Howard S. David | 1996-12-31 |