Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and apparatus for sequencing system bus grants and disabling a posting buffer in a bus bridge to improve bus efficiency

Method and apparatus for sequencing system bus grants and disabling a posting buffer in a bus bridge to improve bus efficiency

US Patent 6026460 · Granted Feb 15, 2000

Estimated economic value: $152,070,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

System and method for receiver equalization and stressed eye testing methodology2024
System and method for receiver equalization and stressed eye testing methodology2023
Stuffing bits on a memory bus between data bursts2016
Digital media player2014
Method and apparatus to limit memory power2014
Method and system to improve the operations of a registered memory module2014
Memory power management via dynamic memory operation states2013
Memory power estimation by means of calibrated weights and activity counters2013
Method and system to improve the operations of a registered memory module2013
Adaptive memory frequency scaling2012
Power management using adaptive thermal throttling2012
Memory rank burst scheduling2011