Issued Patents All Time
Showing 25 most recent of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9262837 | PCIE clock rate stepping for graphics and platform processors | Anthony Michael Tamasi, William P. Tsu, David G. Reed | 2016-02-16 |
| 9098383 | Consolidated crossbar that supports a multitude of traffic types | Sean J. Treichler, Dane T. Mrazek, Yin Fung Tang, David B. Glasco, Emmett M. Kilgariff | 2015-08-04 |
| 8341380 | Efficient memory translator with variable size cache line coverage | James Leroy Deming, Mark Mosley, William Craig McKnight, Emmett M. Kilgrariff, Steven E. Molnar | 2012-12-25 |
| 8161252 | Memory interface with dynamic selection among mirrored storage locations | Anders M. Kugler, Peter C. Tong | 2012-04-17 |
| 8035647 | Raster operations unit with interleaving of read and write requests using PCI express | Donald A. Bittel, Paul D. MacDougal, Manas Mandal | 2011-10-11 |
| 7797510 | Memory management for virtual address space with translation units of variable range size | Gary D. Lorensen, Sharon Rose Clay | 2010-09-14 |
| 7788439 | Asymmetrical bus for bus link width optimization of a graphics system | William P. Tsu | 2010-08-31 |
| 7664905 | Page stream sorter for poor locality access patterns | David Jarosh, Sonny S. Yeoh, John H. Edmondson | 2010-02-16 |
| 7624221 | Control device for data stream optimizations in a link interface | — | 2009-11-24 |
| 7562205 | Virtual address translation system with caching of variable-range translation clusters | Dmitry Vyshetsky, Sean J. Treichler | 2009-07-14 |
| 7526593 | Packet combiner for a packetized bus with dynamic holdoff time | Manas Mandal, William P. Tsu, Ashish Kaul | 2009-04-28 |
| 7469311 | Asymmetrical bus | William P. Tsu | 2008-12-23 |
| 7415575 | Shared cache with client-specific replacement policy | Peter C. Tong | 2008-08-19 |
| 7386697 | Memory management for virtual address space with translation units of variable range size | Gary D. Lorensen, Sharon Rose Clay | 2008-06-10 |
| 7334108 | Multi-client virtual address translation system with translation units of variable-range size | Dmitry Vyshetsky, Sean J. Treichler | 2008-02-19 |
| 7296139 | In-memory table structure for virtual address translation system with translation units of variable range size | Dmitry Vyshetsky | 2007-11-13 |
| 7278008 | Virtual address translation system with caching of variable-range translation clusters | Dmitry Vyshetsky, Sean J. Treichler | 2007-10-02 |
| 6820173 | Data prefetcher with predictor capabilities | Donald A. Bittel | 2004-11-16 |
| 6317803 | High-throughput interconnect having pipelined and non-pipelined bus transaction modes | Norman J. Rasmussen, Gary Solomon, David G. Carson, George R. Hayek, Brent S. Baxter | 2001-11-13 |
| 6097402 | System and method for placement of operands in system memory | Brian K. Langendorf, George R. Hayek, Kim A. Meinerth | 2000-08-01 |
| 6044419 | Memory handling system that backfills dual-port buffer from overflow buffer when dual-port buffer is no longer full | George R. Hayek | 2000-03-28 |
| 5911051 | High-throughput interconnect allowing bus transactions based on partial access requests | David G. Carson, George R. Hayek, Brent S. Baxter, Kim A. Meinerth, Brian K. Langendorf | 1999-06-08 |
| 5321806 | Method and apparatus for transmitting graphics command in a computer graphics system | Kim A. Meinerth, Ali Moezzi, John W. Irwin, Agnes Masucci, Srinivasan Krishnaswami | 1994-06-14 |
| 5321810 | Address method for computer graphics system | Kim A. Meinerth, John W. Irwin, Blaise Fanning | 1994-06-14 |
| 5315696 | Graphics command processing method in a computer graphics system | Kim A. Meinerth, John W. Irwin, Blaise Fanning | 1994-05-24 |