Issued Patents All Time
Showing 1–25 of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6311286 | Symmetric multiprocessing system with unified environment and distributed system functions | James F. Bertone, Bruno DiPlacido, Martin Massucci, Lance J. McNally, Thomas L. Murray, Jr. +6 more | 2001-10-30 |
| 6125436 | Symmetric multiprocessing system with unified environment and distributed system functions wherein bus operations related storage spaces are mapped into a single system address space | James F. Bertone, Bruno DiPlacido, Martin Massucci, Lance J. McNally, Thomas L. Murray, Jr. +6 more | 2000-09-26 |
| 5956522 | Symmetric multiprocessing system with unified environment and distributed system functions | James F. Bertone, Bruno DiPlacido, Martin Massucci, Lance T. McNally, Thomas L. Murray, Jr. +6 more | 1999-09-21 |
| 5809340 | Adaptively generating timing signals for access to various memory devices based on stored profiles | James F. Bertone, Bruno DiPlacido, Martin Massucci, Lance J. McNally, Thomas L. Murray, Jr. +10 more | 1998-09-15 |
| 5522069 | Symmetric multiprocessing system with unified environment and distributed system functions | James F. Bertone, Bruno DiPlacido, Martin Massucci, Lance J. McNally, Thomas L. Murray, Jr. +10 more | 1996-05-28 |
| 5517648 | Symmetric multiprocessing system with unified environment and distributed system functions | James F. Bertone, Bruno DiPlacido, Martin Massucci, Lance J. McNally, Thomas L. Murray, Jr. +6 more | 1996-05-14 |
| 5430862 | Emulation of CISC instructions by RISC instructions using two pipelined stages for overlapped CISC decoding and RISC execution | Steven S. Smith, Arnold J. Smith, Amy E. Gilfeather, Richard P. Brown | 1995-07-04 |
| 5341495 | Bus controller having state machine for translating commands and controlling accesses from system bus to synchronous bus having different bus protocols | James W. Keeley, Richard A. Lemay, Bruno DiPlacido, Martin Massucci | 1994-08-23 |
| 5341508 | Processing unit having multiple synchronous bus for sharing access and regulating system bus access to synchronous bus | James W. Keeley | 1994-08-23 |
| 5287522 | External procedure invocation apparatus utilizing internal branch vector interrupts and vector address generation, in a RISC chip | Richard P. Brown, Steven S. Smith | 1994-02-15 |
| 5283870 | Method and apparatus for avoiding processor deadly embrace in a multiprocessor system | James W. Keeley | 1994-02-01 |
| 5193181 | Recovery method and apparatus for a pipelined processing unit of a multiprocessor system | George J. Barlow, James W. Keeley, Richard A. Lemay, Jian-Kuo Shen, Robert V. Ledoux +2 more | 1993-03-09 |
| 5148530 | Method for reexecuting instruction by altering high bits of instruction address based upon result of a subtraction operation with stored low bits | Richard P. Kelly, Jian-Kuo Shen | 1992-09-15 |
| 5148533 | Apparatus and method for data group coherency in a tightly coupled data processing system with plural execution and data cache units | Robert C. Miller, Marc Vogt | 1992-09-15 |
| 5123097 | Apparatus and method for simultaneous execution of a write instruction and a succeeding read instruction in a data processing system with a store through cache strategy | Ming T. Miu, Richard P. Kelly | 1992-06-16 |
| 5053951 | Segment descriptor unit for performing static and dynamic address translation operations | Eugene B. Nusinov | 1991-10-01 |
| 5051894 | Apparatus and method for address translation of non-aligned double word virtual addresses | Forrest M. Phillips, Ming T. Miu | 1991-09-24 |
| 4942547 | Multiprocessors on a single semiconductor chip | Richard P. Kelly, Jian-Kuo Shen, Michel M. Raguin | 1990-07-17 |
| 4901222 | Method and apparatus for backing out of a software instruction after execution has begun | Richard P. Kelly, Jian-Kuo Shen | 1990-02-13 |
| 4813002 | High speed high density dynamic address translator | Eugene B. Nusinov, Richard P. Brown | 1989-03-14 |
| 4785398 | Virtual cache system using page level number generating CAM to access other memories for processing requests relating to a page | Ming T. Miu, Jian-Kuo Shen, Forrest M. Phillips | 1988-11-15 |
| 4783735 | Least recently used replacement level generating apparatus | Ming T. Miu, Jian-Kuo Shen, Forrest M. Phillips | 1988-11-08 |
| 4695943 | Multiprocessor shared pipeline cache memory with split cycle and concurrent utilization | James W. Keeley | 1987-09-22 |
| 4670835 | Distributed control store word architecture | Richard P. Kelly | 1987-06-02 |
| 4641305 | Control store memory read error resiliency method and apparatus | Richard P. Kelly | 1987-02-03 |