Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5197133 | Control store addressing from multiple sources | Jian-Kuo Shen, Robert V. Ledoux, Deborah K. Staplin | 1993-03-23 |
| 5193181 | Recovery method and apparatus for a pipelined processing unit of a multiprocessor system | George J. Barlow, James W. Keeley, Richard A. Lemay, Jian-Kuo Shen, Robert V. Ledoux +2 more | 1993-03-09 |
| 5179671 | Apparatus for generating first and second selection signals for aligning words of an operand and bytes within these words respectively | Robert V. Ledoux | 1993-01-12 |
| 5148530 | Method for reexecuting instruction by altering high bits of instruction address based upon result of a subtraction operation with stored low bits | Thomas F. Joyce, Jian-Kuo Shen | 1992-09-15 |
| 5123097 | Apparatus and method for simultaneous execution of a write instruction and a succeeding read instruction in a data processing system with a store through cache strategy | Thomas F. Joyce, Ming T. Miu | 1992-06-16 |
| 5117491 | Ring reduction logic using parallel determination of ring numbers in a plurality of functional units and forced ring numbers by instruction decoding | Robert V. Ledoux, Forrest M. Phillips | 1992-05-26 |
| 4980819 | Mechanism for automatically updating multiple unit register file memories in successive cycles for a pipelined processing system | David E. Cushing, Robert V. Ledoux, Jian-Kuo Shen | 1990-12-25 |
| 4942547 | Multiprocessors on a single semiconductor chip | Thomas F. Joyce, Jian-Kuo Shen, Michel M. Raguin | 1990-07-17 |
| 4916601 | Means for transferring firmware signals between a control store and a microprocessor means through a reduced number of connections by transfer according to firmware signal function | Jian-Kuo Shen, Robert V. Ledoux, Chester M. Nibby, Jr. | 1990-04-10 |
| 4901222 | Method and apparatus for backing out of a software instruction after execution has begun | Thomas F. Joyce, Jian-Kuo Shen | 1990-02-13 |
| 4670835 | Distributed control store word architecture | Thomas F. Joyce | 1987-06-02 |
| 4641305 | Control store memory read error resiliency method and apparatus | Thomas F. Joyce | 1987-02-03 |
| 4494186 | Automatic data steering and data formatting mechanism | Gary J. Goss, Thomas L. Murray, Jr. | 1985-01-15 |
| 4458308 | Microprocessor controlled communications controller having a stretched clock cycle | Thomas O. Holtey, Steven Noyes | 1984-07-03 |
| 4418384 | Communication subsystem with an automatic abort transmission upon transmit underrun | Thomas O. Holtey, Steven Noyes, James C. Raymond | 1983-11-29 |
| 4407014 | Communications subsystem having a direct connect clock | Thomas O. Holtey, Daniel G. Peters | 1983-09-27 |
| 4379340 | Communications subsystem idle link state detector | Thomas O. Holtey, Steven Noyes, James C. Raymond | 1983-04-05 |
| 4254462 | Hardware/firmware communication line adapter | James C. Raymond, Richard A. Lemay | 1981-03-03 |