Issued Patents All Time
Showing 1–25 of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5850521 | Apparatus and method for interprocessor communication | Victor M. Morganti, Patrick E. Prange, James B. Geyer | 1998-12-15 |
| 5664200 | Apparatus and method for providing more effective reiterations of interrupt requests in a multiprocessor system | James W. Keeley | 1997-09-02 |
| 5446847 | Programmable system bus priority network | James W. Keeley, Richard A. Lemay | 1995-08-29 |
| 5404535 | Apparatus and method for providing more effective reiterations of processing task requests in a multiprocessor system | James W. Keeley | 1995-04-04 |
| 5379378 | Data processing system having a bus command generated by one subsystem on behalf of another subsystem | Arthur Peters, Richard C. Zelley, Elmer W. Carroll, Chester M. Nibby, Jr., James W. Keeley | 1995-01-03 |
| 5367697 | Means for providing a graceful power shut-down capability in a multiprocessor system having certain processors not inherently having a power shut-down capability | James W. Keeley | 1994-11-22 |
| 5274797 | Multiprocessor system with centralized initialization, testing and monitoring of the system and providing centralized timing | Elmer W. Carroll, James W. Keeley, Wallace A. Martland, Victor M. Morganti, Arthur Peters +1 more | 1993-12-28 |
| 5243702 | Minimum contention processor and system bus system | Donald L. Smith | 1993-09-07 |
| 5241629 | Method and apparatus for a high performance round robin distributed bus priority network | Donald L. Smith | 1993-08-31 |
| 5210757 | Method and apparatus for performing health tests of units of a data processing system | Richard C. Zelley, James W. Keeley | 1993-05-11 |
| 5210867 | Method and apparatus for memory retry | Raymond D. Bowden, III, Michelle A. Pence | 1993-05-11 |
| 5204964 | Method and apparatus for resetting a memory upon power recovery | Raymond D. Bowden, III, Michelle A. Pence, Marc Sanfacon, Jeffrey S. Somers | 1993-04-20 |
| 5193181 | Recovery method and apparatus for a pipelined processing unit of a multiprocessor system | James W. Keeley, Richard A. Lemay, Jian-Kuo Shen, Robert V. Ledoux, Thomas F. Joyce +2 more | 1993-03-09 |
| 5168564 | Cancel mechanism for resilient resource management and control | Donald L. Smith | 1992-12-01 |
| 5150466 | Flexible distributed bus priority network | Donald L. Smith | 1992-09-22 |
| 5099420 | Method and apparatus for limiting the utilization of an asynchronous bus with distributed controlled access | John W. Bradley, Edward F. Getson, Jr. | 1992-03-24 |
| 4992930 | Synchronous cache memory system incorporating tie-breaker apparatus for maintaining cache coherency using a duplicate directory | Amy E. Gilfeather | 1991-02-12 |
| 4932040 | Bidirectional control signalling bus interface apparatus for transmitting signals between two bus systems | — | 1990-06-05 |
| 4910666 | Apparatus for loading and verifying a control store memory of a central subsystem | Chester M. Nibby, Jr., Richard C. Zelley, Kenneth E. Bruce, James W. Keeley | 1990-03-20 |
| 4901226 | Inter and intra priority resolution network for an asynchronous bus system | — | 1990-02-13 |
| 4839800 | Data processing system with a fast interrupt | James W. Keeley | 1989-06-13 |
| 4833601 | Cache resiliency in processing a variety of address faults | James W. Keeley, Chester M. Nibby, Jr. | 1989-05-23 |
| 4802087 | Multiprocessor level change synchronization apparatus | James W. Keeley | 1989-01-31 |
| 4799222 | Address transform method and apparatus for transferring addresses | James W. Keeley, Chester M. Nibby, Jr. | 1989-01-17 |
| 4768148 | Read in process memory apparatus | James W. Keeley | 1988-08-30 |