Issued Patents All Time
Showing 1–25 of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6311286 | Symmetric multiprocessing system with unified environment and distributed system functions | James F. Bertone, Bruno DiPlacido, Thomas F. Joyce, Martin Massucci, Lance J. McNally +6 more | 2001-10-30 |
| 6125436 | Symmetric multiprocessing system with unified environment and distributed system functions wherein bus operations related storage spaces are mapped into a single system address space | James F. Bertone, Bruno DiPlacido, Thomas F. Joyce, Martin Massucci, Lance J. McNally +6 more | 2000-09-26 |
| 5956522 | Symmetric multiprocessing system with unified environment and distributed system functions | James F. Bertone, Bruno DiPlacido, Thomas F. Joyce, Martin Massucci, Lance T. McNally +6 more | 1999-09-21 |
| 5809340 | Adaptively generating timing signals for access to various memory devices based on stored profiles | James F. Bertone, Bruno DiPlacido, Thomas F. Joyce, Martin Massucci, Lance J. McNally +10 more | 1998-09-15 |
| 5522069 | Symmetric multiprocessing system with unified environment and distributed system functions | James F. Bertone, Bruno DiPlacido, Thomas F. Joyce, Martin Massucci, Lance J. McNally +10 more | 1996-05-28 |
| 5517648 | Symmetric multiprocessing system with unified environment and distributed system functions | James F. Bertone, Bruno DiPlacido, Thomas F. Joyce, Martin Massucci, Lance J. McNally +6 more | 1996-05-14 |
| 5491790 | Power-on sequencing apparatus for initializing and testing a system processing unit | James W. Keeley, Richard A. Lemay, Keith L. Petry, Thomas S. Hirsch | 1996-02-13 |
| 5379378 | Data processing system having a bus command generated by one subsystem on behalf of another subsystem | Arthur Peters, Richard C. Zelley, Elmer W. Carroll, George J. Barlow, James W. Keeley | 1995-01-03 |
| 5345573 | High speed burst read address generation with high speed transfer | Raymond D. Bowden, III | 1994-09-06 |
| 5341501 | Processor bus access | James W. Keeley, Richard A. Lemay | 1994-08-23 |
| 5291580 | High performance burst read data transfer operation | Raymond D. Bowden, III, Richard A. Lemay, Jeffrey S. Somers | 1994-03-01 |
| 4916601 | Means for transferring firmware signals between a control store and a microprocessor means through a reduced number of connections by transfer according to firmware signal function | Richard P. Kelly, Jian-Kuo Shen, Robert V. Ledoux | 1990-04-10 |
| 4910666 | Apparatus for loading and verifying a control store memory of a central subsystem | Richard C. Zelley, Kenneth E. Bruce, George J. Barlow, James W. Keeley | 1990-03-20 |
| 4833601 | Cache resiliency in processing a variety of address faults | George J. Barlow, James W. Keeley | 1989-05-23 |
| 4799222 | Address transform method and apparatus for transferring addresses | George J. Barlow, James W. Keeley | 1989-01-17 |
| 4558429 | Pause apparatus for a memory controller with interleaved queuing apparatus | George J. Barlow, Robert B. Johnson | 1985-12-10 |
| 4545010 | Memory identification apparatus and method | Edward R. Salas, Edwin P. Fisher, Robert B. Johnson, Daniel Boudreau | 1985-10-01 |
| 4527251 | Remap method and apparatus for a memory system which uses partially good memory devices | Reeni Goldin, Timothy A. Andrews | 1985-07-02 |
| 4523313 | Partial defective chip memory support system | Reeni Goldin, Timothy A. Andrews | 1985-06-11 |
| 4507730 | Memory system with automatic memory configuration | Robert B. Johnson, Edward R. Salas | 1985-03-26 |
| 4468731 | Identification apparatus for use in a controller to facilitate the diagnosis of faults | Robert B. Johnson, Edward R. Salas | 1984-08-28 |
| 4451880 | Memory controller with interleaved queuing apparatus | Robert B. Johnson | 1984-05-29 |
| 4432055 | Sequential word aligned addressing apparatus | Edward R. Salas, Robert B. Johnson | 1984-02-14 |
| 4388684 | Apparatus for deferring error detection of multibyte parity encoded data received from a plurality of input/output data sources | Robert B. Johnson | 1983-06-14 |
| 4376972 | Sequential word aligned address apparatus | Robert B. Johnson, Dana W. Moore | 1983-03-15 |