Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 4964129 | Memory controller with error logging | Raymond D. Bowden, III, Marc Sanfacon, Jeffrey S. Somers | 1990-10-16 |
| 4964130 | System for determining status of errors in a memory subsystem | Raymond D. Bowden, III, Marc Sanfacon, Jeffrey S. Somers | 1990-10-16 |
| 4787060 | Technique for determining maximum physical memory present in a system and for detecting attempts to access nonexistent memory | Daniel Boudreau | 1988-11-22 |
| 4654788 | Asynchronous multiport parallel access memory system for use in a single board computer system | Daniel Boudreau | 1987-03-31 |
| 4600992 | Priority resolver with lowest priority level having shortest logic path | Daniel Boudreau | 1986-07-15 |
| 4587609 | Lockout operation among asynchronous accessers of a shared computer system resource | Daniel Boudreau, James M. Sandini | 1986-05-06 |
| 4563736 | Memory architecture for facilitating optimum replaceable unit (ORU) detection and diagnosis | Daniel Boudreau, Richard C. Zelley | 1986-01-07 |
| 4559595 | Distributed priority network logic for allowing a low priority unit to reside in a high priority position | Daniel Boudreau, James M. Sandini | 1985-12-17 |
| 4545010 | Memory identification apparatus and method | Edwin P. Fisher, Robert B. Johnson, Chester M. Nibby, Jr., Daniel Boudreau | 1985-10-01 |
| 4507730 | Memory system with automatic memory configuration | Robert B. Johnson, Chester M. Nibby, Jr. | 1985-03-26 |
| 4493036 | Priority resolver having dynamically adjustable priority levels | Daniel Boudreau | 1985-01-08 |
| 4468731 | Identification apparatus for use in a controller to facilitate the diagnosis of faults | Robert B. Johnson, Chester M. Nibby, Jr. | 1984-08-28 |
| 4432055 | Sequential word aligned addressing apparatus | Chester M. Nibby, Jr., Robert B. Johnson | 1984-02-14 |